[PATCH] D153748: [RISCV] Add support for XCValu extension in CV32E40P
QIHAN CAI via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 7 02:32:31 PDT 2023
realqhc updated this revision to Diff 538044.
realqhc marked 4 inline comments as done.
realqhc added a comment.
update ISA version accordingly
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D153748/new/
https://reviews.llvm.org/D153748
Files:
llvm/docs/RISCVUsage.rst
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
llvm/test/MC/RISCV/corev/XCValu-invalid.s
llvm/test/MC/RISCV/corev/XCValu-valid.s
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