[PATCH] D153842: [PowerPC] Update input operands information of Power10 scheduling model

[ChenZheng via Phabricator via llvm-commits]

shchenz accepted this revision as: shchenz.
shchenz added a comment.
This revision is now accepted and ready to land.

LGTM.



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Comment at: llvm/lib/Target/PowerPC/P10InstrResources.td:317
+    BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL,
+    BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR,
+    BCLRL, BCLRLn, BDNZLRL, BDNZLRLm, BDNZLRLp, BDZLRL, BDZLRLm, BDZLRLp, gBCLRL,
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qiucf wrote:
> shchenz wrote:
> > I am not familiar with the syntax here. But seems from the td file:
> > ```
> >    def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
> >                              "bdnzlr", IIC_BrB, []>;
> > ```
> > 
> > BDNZLR should have 0 input operands. But after the change, we now treat it as 1 input operand. Do you know why?
> `bdnzlr` is actually mnemonic of `bclr`:
> 
> > Extended mnemonic:
> > bclr 4,6 Equivalent to bclr 4,6,0
> > bltlr Equivalent to bclr 12,0,0
> > bnelr cr2 Equivalent to bclr 4,10,0
> > bdnzlr Equivalent to bclr 16,0,0
> 
> ```
> def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI),
>                          "bclr 12, $BI, 0", IIC_BrB, []>;
> ```
I see. Thanks for checking.


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https://reviews.llvm.org/D153842