[PATCH] D154679: [RISCV] Rename prefix `fixed-vector` to `fixed-vectors` to be the same with other testcases

[Jim Lin via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG43927542d836: [RISCV] Rename prefix `fixed-vector` to `fixed-vectors` to be the same with… (authored by Jim).

Changed prior to commit:
  https://reviews.llvm.org/D154679?vs=537969&id=537986#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154679/new/

https://reviews.llvm.org/D154679

Files:
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-inttoptr-ptrtoint.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-transpose.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-vslide1down.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-vslide1up.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-negative.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-segN-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-negative.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll