[llvm] 64df957 - DAG: Handle inversion of fcSubnormal | fcZero
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 6 18:19:49 PDT 2023
Author: Matt Arsenault
Date: 2023-07-06T21:19:44-04:00
New Revision: 64df9573a7ab0ab4a0743978086a8bfd1380a238
URL: https://github.com/llvm/llvm-project/commit/64df9573a7ab0ab4a0743978086a8bfd1380a238
DIFF: https://github.com/llvm/llvm-project/commit/64df9573a7ab0ab4a0743978086a8bfd1380a238.diff
LOG: DAG: Handle inversion of fcSubnormal | fcZero
There are a number of more test combinations here that
can be done together and reduce the number of instructions.
https://reviews.llvm.org/D143191
Added:
Modified:
llvm/include/llvm/CodeGen/CodeGenCommonISel.h
llvm/lib/CodeGen/CodeGenCommonISel.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
llvm/test/CodeGen/X86/is_fpclass.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/CodeGenCommonISel.h b/llvm/include/llvm/CodeGen/CodeGenCommonISel.h
index d08ddbfa7c1334..90ef890f22d1b1 100644
--- a/llvm/include/llvm/CodeGen/CodeGenCommonISel.h
+++ b/llvm/include/llvm/CodeGen/CodeGenCommonISel.h
@@ -214,13 +214,14 @@ class StackProtectorDescriptor {
MachineBasicBlock::iterator
findSplitPointForStackProtector(MachineBasicBlock *BB,
const TargetInstrInfo &TII);
-/// Evaluates if the specified FP class test is an inversion of a simpler test.
-/// An example is the test "inf|normal|subnormal|zero", which is an inversion
-/// of "nan".
+
+/// Evaluates if the specified FP class test is better performed as the inverse
+/// (i.e. fewer instructions should be required to lower it). An example is the
+/// test "inf|normal|subnormal|zero", which is an inversion of "nan".
/// \param Test The test as specified in 'is_fpclass' intrinsic invocation.
-/// \returns The inverted test, or zero, if inversion does not produce simpler
-/// test.
-FPClassTest getInvertedFPClassTest(FPClassTest Test);
+/// \returns The inverted test, or fcNone, if inversion does not produce a
+/// simpler test.
+FPClassTest invertFPClassTestIfSimpler(FPClassTest Test);
/// Assuming the instruction \p MI is going to be deleted, attempt to salvage
/// debug users of \p MI by writing the effect of \p MI in a DIExpression.
diff --git a/llvm/lib/CodeGen/CodeGenCommonISel.cpp b/llvm/lib/CodeGen/CodeGenCommonISel.cpp
index 2b653f0b901488..62613c00737981 100644
--- a/llvm/lib/CodeGen/CodeGenCommonISel.cpp
+++ b/llvm/lib/CodeGen/CodeGenCommonISel.cpp
@@ -173,11 +173,11 @@ llvm::findSplitPointForStackProtector(MachineBasicBlock *BB,
return SplitPoint;
}
-FPClassTest llvm::getInvertedFPClassTest(FPClassTest Test) {
- FPClassTest InvertedTest = ~Test & fcAllFlags;
- switch (InvertedTest) {
- default:
- break;
+FPClassTest llvm::invertFPClassTestIfSimpler(FPClassTest Test) {
+ FPClassTest InvertedTest = ~Test;
+ // Pick the direction with fewer tests
+ // TODO: Handle more combinations of cases that can be handled together
+ switch (static_cast<unsigned>(InvertedTest)) {
case fcNan:
case fcSNan:
case fcQNan:
@@ -196,9 +196,13 @@ FPClassTest llvm::getInvertedFPClassTest(FPClassTest Test) {
case fcFinite:
case fcPosFinite:
case fcNegFinite:
+ case fcSubnormal | fcZero:
return InvertedTest;
+ default:
+ return fcNone;
}
- return fcNone;
+
+ llvm_unreachable("covered FPClassTest");
}
static MachineOperand *getSalvageOpsForCopy(const MachineRegisterInfo &MRI,
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index ef723fd4079499..e1296e69447944 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8060,6 +8060,7 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
/// for the floating-point mode.
static bool isFCmpEqualZero(FPClassTest Test, const fltSemantics &Semantics,
const MachineFunction &MF) {
+ // TODO: Handle unordered compares
if (Test == fcZero &&
MF.getDenormalMode(Semantics).Input == DenormalMode::IEEE)
return true;
@@ -8093,7 +8094,7 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
// Some checks may be represented as inversion of simpler check, for example
// "inf|normal|subnormal|zero" => !"nan".
bool IsInverted = false;
- if (FPClassTest InvertedCheck = getInvertedFPClassTest(Test)) {
+ if (FPClassTest InvertedCheck = invertFPClassTestIfSimpler(Test)) {
IsInverted = true;
Test = InvertedCheck;
}
@@ -8207,8 +8208,6 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
// fcZero | fcSubnormal => test all exponent bits are 0
// TODO: Handle sign bit specific cases
if (PartialCheck == (fcZero | fcSubnormal)) {
- assert(!IsInverted && "should handle inverted case");
-
SDValue ExpBits = DAG.getNode(ISD::AND, DL, IntVT, OpAsInt, ExpMaskV);
SDValue ExpIsZero =
DAG.getSetCC(DL, ResultVT, ExpBits, ZeroV, ISD::SETEQ);
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index 4a08b083ff12a9..aa7f6bf3b9d572 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -1557,15 +1557,9 @@ define i1 @not_issubnormal_or_zero_f16(half %x) {
; GFX7SELDAG: ; %bb.0: ; %entry
; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7bff
-; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
-; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s4, v0
-; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
-; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
-; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
-; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7c00, v0
+; GFX7SELDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX7GLISEL-LABEL: not_issubnormal_or_zero_f16:
diff --git a/llvm/test/CodeGen/X86/is_fpclass.ll b/llvm/test/CodeGen/X86/is_fpclass.ll
index 0e80a4dc7aeba7..09ad6adc9352fd 100644
--- a/llvm/test/CodeGen/X86/is_fpclass.ll
+++ b/llvm/test/CodeGen/X86/is_fpclass.ll
@@ -846,26 +846,15 @@ entry:
define i1 @not_issubnormal_or_zero_f(float %x) {
; CHECK-32-LABEL: not_issubnormal_or_zero_f:
; CHECK-32: # %bb.0: # %entry
-; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; CHECK-32-NEXT: setge %cl
-; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; CHECK-32-NEXT: setb %al
-; CHECK-32-NEXT: orb %cl, %al
+; CHECK-32-NEXT: testl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
+; CHECK-32-NEXT: setne %al
; CHECK-32-NEXT: retl
;
; CHECK-64-LABEL: not_issubnormal_or_zero_f:
; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: movd %xmm0, %eax
-; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; CHECK-64-NEXT: setge %cl
-; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; CHECK-64-NEXT: setb %al
-; CHECK-64-NEXT: orb %cl, %al
+; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; CHECK-64-NEXT: setne %al
; CHECK-64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
@@ -875,26 +864,15 @@ entry:
define i1 @not_issubnormal_or_zero_f_daz(float %x) #0 {
; CHECK-32-LABEL: not_issubnormal_or_zero_f_daz:
; CHECK-32: # %bb.0: # %entry
-; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; CHECK-32-NEXT: setge %cl
-; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; CHECK-32-NEXT: setb %al
-; CHECK-32-NEXT: orb %cl, %al
+; CHECK-32-NEXT: testl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
+; CHECK-32-NEXT: setne %al
; CHECK-32-NEXT: retl
;
; CHECK-64-LABEL: not_issubnormal_or_zero_f_daz:
; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: movd %xmm0, %eax
-; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; CHECK-64-NEXT: setge %cl
-; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; CHECK-64-NEXT: setb %al
-; CHECK-64-NEXT: orb %cl, %al
+; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; CHECK-64-NEXT: setne %al
; CHECK-64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
@@ -904,26 +882,15 @@ entry:
define i1 @not_issubnormal_or_zero_f_maybe_daz(float %x) #1 {
; CHECK-32-LABEL: not_issubnormal_or_zero_f_maybe_daz:
; CHECK-32: # %bb.0: # %entry
-; CHECK-32-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-32-NEXT: andl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; CHECK-32-NEXT: setge %cl
-; CHECK-32-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; CHECK-32-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; CHECK-32-NEXT: setb %al
-; CHECK-32-NEXT: orb %cl, %al
+; CHECK-32-NEXT: testl $2139095040, {{[0-9]+}}(%esp) # imm = 0x7F800000
+; CHECK-32-NEXT: setne %al
; CHECK-32-NEXT: retl
;
; CHECK-64-LABEL: not_issubnormal_or_zero_f_maybe_daz:
; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: movd %xmm0, %eax
-; CHECK-64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-64-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000
-; CHECK-64-NEXT: setge %cl
-; CHECK-64-NEXT: addl $-8388608, %eax # imm = 0xFF800000
-; CHECK-64-NEXT: cmpl $2130706432, %eax # imm = 0x7F000000
-; CHECK-64-NEXT: setb %al
-; CHECK-64-NEXT: orb %cl, %al
+; CHECK-64-NEXT: testl $2139095040, %eax # imm = 0x7F800000
+; CHECK-64-NEXT: setne %al
; CHECK-64-NEXT: retq
entry:
%0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
More information about the llvm-commits
mailing list