[llvm] be253cb - [RISCV] Support i32 brev8 intrinsic on RV64.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-06T17:24:53-07:00
New Revision: be253cb987a9fa078c66038d2325f81eeacf7209

URL: https://github.com/llvm/llvm-project/commit/be253cb987a9fa078c66038d2325f81eeacf7209
DIFF: https://github.com/llvm/llvm-project/commit/be253cb987a9fa078c66038d2325f81eeacf7209.diff

LOG: [RISCV] Support i32 brev8 intrinsic on RV64.

Similar to what we do for orc.b. Another patch will expose this
as a builtin in clang.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0bfa277f083df0..43d95705cb6433 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9749,10 +9749,13 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       return;
     }
-    case Intrinsic::riscv_orc_b: {
+    case Intrinsic::riscv_orc_b:
+    case Intrinsic::riscv_brev8: {
+      unsigned Opc =
+          IntNo == Intrinsic::riscv_brev8 ? RISCVISD::BREV8 : RISCVISD::ORC_B;
       SDValue NewOp =
           DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue Res = DAG.getNode(RISCVISD::ORC_B, DL, MVT::i64, NewOp);
+      SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       return;
     }

diff  --git a/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
index d3ba14c71cb929..3169f65f646718 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbkb-intrinsic.ll
@@ -2,14 +2,14 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64ZBKB
 
-declare i64 @llvm.riscv.brev8(i64)
+declare i64 @llvm.riscv.brev8.i64(i64)
 
 define i64 @brev8(i64 %a) nounwind {
 ; RV64ZBKB-LABEL: brev8:
 ; RV64ZBKB:       # %bb.0:
 ; RV64ZBKB-NEXT:    brev8 a0, a0
 ; RV64ZBKB-NEXT:    ret
-  %val = call i64 @llvm.riscv.brev8(i64 %a)
+  %val = call i64 @llvm.riscv.brev8.i64(i64 %a)
   ret i64 %val
 }
 
@@ -20,7 +20,7 @@ define zeroext i16 @brev8_knownbits(i16 zeroext %a) nounwind {
 ; RV64ZBKB-NEXT:    brev8 a0, a0
 ; RV64ZBKB-NEXT:    ret
   %zext = zext i16 %a to i64
-  %val = call i64 @llvm.riscv.brev8(i64 %zext)
+  %val = call i64 @llvm.riscv.brev8.i64(i64 %zext)
   %trunc = trunc i64 %val to i16
   ret i16 %trunc
 }
@@ -35,3 +35,39 @@ define i64 @rev8_i64(i64 %a) {
   %1 = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %1
 }
+
+declare i32 @llvm.riscv.brev8.i32(i32)
+
+define signext i32 @brev8_i32(i32 signext %a) nounwind {
+; RV64ZBKB-LABEL: brev8_i32:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    brev8 a0, a0
+; RV64ZBKB-NEXT:    sext.w a0, a0
+; RV64ZBKB-NEXT:    ret
+  %val = call i32 @llvm.riscv.brev8.i32(i32 %a)
+  ret i32 %val
+}
+
+; Test that rev8 is recognized as preserving zero extension.
+define zeroext i16 @brev8_i32_knownbits(i16 zeroext %a) nounwind {
+; RV64ZBKB-LABEL: brev8_i32_knownbits:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    brev8 a0, a0
+; RV64ZBKB-NEXT:    ret
+  %zext = zext i16 %a to i32
+  %val = call i32 @llvm.riscv.brev8.i32(i32 %zext)
+  %trunc = trunc i32 %val to i16
+  ret i16 %trunc
+}
+
+declare i32 @llvm.bswap.i32(i32)
+
+define signext i32 @rev8_i32(i32 signext %a) {
+; RV64ZBKB-LABEL: rev8_i32:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    rev8 a0, a0
+; RV64ZBKB-NEXT:    srai a0, a0, 32
+; RV64ZBKB-NEXT:    ret
+  %1 = call i32 @llvm.bswap.i32(i32 %a)
+  ret i32 %1
+}