[PATCH] D154142: [llvm-mca][RISCV] Add RISCV-SEW instrument

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland planned changes to this revision.
michaelmaitland added inline comments.


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Comment at: llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s:31
 # CHECK-NEXT:  1      3     1.00                  U     vsetvli	zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  1      4     2.00                        vadd.vv	v12, v12, v12
+# CHECK-NEXT:  1      4     16.00                       vadd.vv	v12, v12, v12
 # CHECK-NEXT:  1      3     1.00                  U     vsetvli	zero, a0, e8, m8, tu, mu
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It looks like we're defaulting to worst case when SEW is provided, but the sched resource does not depend on SEW. This is occurring in many of the test cases. I need to fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154142/new/

https://reviews.llvm.org/D154142