[PATCH] D152726: [RISCV][GlobalISel] Legalize all ALU instructions, excluding w-instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:79
+  getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
+      .legalFor({XLenLLT})
+      .clampScalar(0, XLenLLT, XLenLLT)
----------------
tschuett wrote:
> craig.topper wrote:
> > How can G_ZEXT/G_SEXT/G_ANYEXT be legal for any types? The source and destination should be different types, and there is only 1 legal type on RISC-V.
> The most complete target for Gisel is AArch64. See there legalisation for EXTs:
> https://github.com/llvm/llvm-project/blob/f70967fdc4736a5c5150db294be55fa9e7792bb8/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp#L513
I think the AArch64 rules are over-permissive and old. It shouldn't be permitting <= register size, only == register size values through


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152726/new/

https://reviews.llvm.org/D152726