[PATCH] D154536: [RISCV] Check for alignment when lowering interleaved/deinterleaved loads/stores

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll:43
+; CHECK-NEXT:    vwmaccu.vx v12, a1, v10
+; CHECK-NEXT:    vs4r.v v12, (a0)
 ; CHECK-NEXT:    ret
----------------
Amusingly, this is still wrong by the alignment rule.

"Implementations are allowed to raise a misaligned address exception on whole register loads and stores if the base address
is not naturally aligned to the larger of the size of the encoded EEW in bytes (EEW/8) or the implementation’s smallest
supported SEW size in bytes (SEW MIN /8)."

But this has nothing to do with the segment load/store lowering stuff.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154536/new/

https://reviews.llvm.org/D154536