[llvm] c70cae6 - AMDGPU: Make SIFixVGPRCopies preserve everything

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2023-07-06T10:26:21-04:00
New Revision: c70cae6315f30edc910f0fa46cfa39bc25051652

URL: https://github.com/llvm/llvm-project/commit/c70cae6315f30edc910f0fa46cfa39bc25051652
DIFF: https://github.com/llvm/llvm-project/commit/c70cae6315f30edc910f0fa46cfa39bc25051652.diff

LOG: AMDGPU: Make SIFixVGPRCopies preserve everything

All this does is add uses of reserved registers, which
aren't tracked by anything. Saves a loop info computation.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp
    llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp
index f7e3ea5fc0723c..08272a9ddfd307 100644
--- a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp
@@ -31,6 +31,11 @@ class SIFixVGPRCopies : public MachineFunctionPass {
     initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry());
   }
 
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesAll();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   StringRef getPassName() const override { return "SI Fix VGPR copies"; }

diff  --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index b9423700ea1f5f..9eb52e40f683f6 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -377,9 +377,8 @@
 ; GCN-O1-NEXT:        Remove Redundant DEBUG_VALUE analysis
 ; GCN-O1-NEXT:        Fixup Statepoint Caller Saved
 ; GCN-O1-NEXT:        PostRA Machine Sink
-; GCN-O1-NEXT:        MachineDominator Tree Construction
-; GCN-O1-NEXT:        Machine Natural Loop Construction
 ; GCN-O1-NEXT:        Machine Block Frequency Analysis
+; GCN-O1-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-NEXT:        MachinePostDominator Tree Construction
 ; GCN-O1-NEXT:        Lazy Machine Block Frequency Analysis
 ; GCN-O1-NEXT:        Machine Optimization Remark Emitter
@@ -676,9 +675,8 @@
 ; GCN-O1-OPTS-NEXT:        Remove Redundant DEBUG_VALUE analysis
 ; GCN-O1-OPTS-NEXT:        Fixup Statepoint Caller Saved
 ; GCN-O1-OPTS-NEXT:        PostRA Machine Sink
-; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
-; GCN-O1-OPTS-NEXT:        Machine Natural Loop Construction
 ; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
+; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-OPTS-NEXT:        MachinePostDominator Tree Construction
 ; GCN-O1-OPTS-NEXT:        Lazy Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Optimization Remark Emitter
@@ -985,9 +983,8 @@
 ; GCN-O2-NEXT:        Remove Redundant DEBUG_VALUE analysis
 ; GCN-O2-NEXT:        Fixup Statepoint Caller Saved
 ; GCN-O2-NEXT:        PostRA Machine Sink
-; GCN-O2-NEXT:        MachineDominator Tree Construction
-; GCN-O2-NEXT:        Machine Natural Loop Construction
 ; GCN-O2-NEXT:        Machine Block Frequency Analysis
+; GCN-O2-NEXT:        MachineDominator Tree Construction
 ; GCN-O2-NEXT:        MachinePostDominator Tree Construction
 ; GCN-O2-NEXT:        Lazy Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        Machine Optimization Remark Emitter
@@ -1306,9 +1303,8 @@
 ; GCN-O3-NEXT:        Remove Redundant DEBUG_VALUE analysis
 ; GCN-O3-NEXT:        Fixup Statepoint Caller Saved
 ; GCN-O3-NEXT:        PostRA Machine Sink
-; GCN-O3-NEXT:        MachineDominator Tree Construction
-; GCN-O3-NEXT:        Machine Natural Loop Construction
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis
+; GCN-O3-NEXT:        MachineDominator Tree Construction
 ; GCN-O3-NEXT:        MachinePostDominator Tree Construction
 ; GCN-O3-NEXT:        Lazy Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        Machine Optimization Remark Emitter