[llvm] c63be92 - [GlobalISel][X86] Regenerate add/sub legalization tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 6 06:09:27 PDT 2023
Author: Simon Pilgrim
Date: 2023-07-06T14:09:11+01:00
New Revision: c63be92fc80c70d56f22abc5aa024ab957f8d4cd
URL: https://github.com/llvm/llvm-project/commit/c63be92fc80c70d56f22abc5aa024ab957f8d4cd
DIFF: https://github.com/llvm/llvm-project/commit/c63be92fc80c70d56f22abc5aa024ab957f8d4cd.diff
LOG: [GlobalISel][X86] Regenerate add/sub legalization tests
Added:
Modified:
llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
index b149fbbe2d3d01..a590410583db88 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
@@ -52,6 +52,7 @@ body: |
; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>)
; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
; SSE2-NEXT: RET 0
+ ;
; AVX1-LABEL: name: test_add_v32i8
; AVX1: liveins: $ymm0, $ymm1
; AVX1-NEXT: {{ $}}
@@ -64,6 +65,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>)
; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
; AVX1-NEXT: RET 0
+ ;
; AVX2-LABEL: name: test_add_v32i8
; AVX2: liveins: $ymm0, $ymm1
; AVX2-NEXT: {{ $}}
@@ -104,6 +106,7 @@ body: |
; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>)
; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
; SSE2-NEXT: RET 0
+ ;
; AVX1-LABEL: name: test_add_v16i16
; AVX1: liveins: $ymm0, $ymm1
; AVX1-NEXT: {{ $}}
@@ -116,6 +119,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>)
; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
; AVX1-NEXT: RET 0
+ ;
; AVX2-LABEL: name: test_add_v16i16
; AVX2: liveins: $ymm0, $ymm1
; AVX2-NEXT: {{ $}}
@@ -156,6 +160,7 @@ body: |
; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>)
; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
; SSE2-NEXT: RET 0
+ ;
; AVX1-LABEL: name: test_add_v8i32
; AVX1: liveins: $ymm0, $ymm1
; AVX1-NEXT: {{ $}}
@@ -168,6 +173,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>)
; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
; AVX1-NEXT: RET 0
+ ;
; AVX2-LABEL: name: test_add_v8i32
; AVX2: liveins: $ymm0, $ymm1
; AVX2-NEXT: {{ $}}
@@ -208,6 +214,7 @@ body: |
; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>)
; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
; SSE2-NEXT: RET 0
+ ;
; AVX1-LABEL: name: test_add_v4i64
; AVX1: liveins: $ymm0, $ymm1
; AVX1-NEXT: {{ $}}
@@ -220,6 +227,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>)
; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
; AVX1-NEXT: RET 0
+ ;
; AVX2-LABEL: name: test_add_v4i64
; AVX2: liveins: $ymm0, $ymm1
; AVX2-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
index 8d9d5cb76105d2..15c7b502779e20 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
@@ -58,6 +58,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>), [[ADD2]](<16 x s8>), [[ADD3]](<16 x s8>)
; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
; AVX1-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_add_v64i8
; AVX512F: liveins: $zmm0, $zmm1
; AVX512F-NEXT: {{ $}}
@@ -70,6 +71,7 @@ body: |
; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[ADD]](<32 x s8>), [[ADD1]](<32 x s8>)
; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
; AVX512F-NEXT: RET 0
+ ;
; AVX512BW-LABEL: name: test_add_v64i8
; AVX512BW: liveins: $zmm0, $zmm1
; AVX512BW-NEXT: {{ $}}
@@ -112,6 +114,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>), [[ADD2]](<8 x s16>), [[ADD3]](<8 x s16>)
; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
; AVX1-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_add_v32i16
; AVX512F: liveins: $zmm0, $zmm1
; AVX512F-NEXT: {{ $}}
@@ -124,6 +127,7 @@ body: |
; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[ADD]](<16 x s16>), [[ADD1]](<16 x s16>)
; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
; AVX512F-NEXT: RET 0
+ ;
; AVX512BW-LABEL: name: test_add_v32i16
; AVX512BW: liveins: $zmm0, $zmm1
; AVX512BW-NEXT: {{ $}}
@@ -166,6 +170,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>), [[ADD2]](<4 x s32>), [[ADD3]](<4 x s32>)
; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
; AVX1-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_add_v16i32
; AVX512F: liveins: $zmm0, $zmm1
; AVX512F-NEXT: {{ $}}
@@ -174,6 +179,7 @@ body: |
; AVX512F-NEXT: [[ADD:%[0-9]+]]:_(<16 x s32>) = G_ADD [[DEF]], [[DEF1]]
; AVX512F-NEXT: $zmm0 = COPY [[ADD]](<16 x s32>)
; AVX512F-NEXT: RET 0
+ ;
; AVX512BW-LABEL: name: test_add_v16i32
; AVX512BW: liveins: $zmm0, $zmm1
; AVX512BW-NEXT: {{ $}}
@@ -216,6 +222,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>), [[ADD2]](<2 x s64>), [[ADD3]](<2 x s64>)
; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
; AVX1-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_add_v8i64
; AVX512F: liveins: $zmm0, $zmm1
; AVX512F-NEXT: {{ $}}
@@ -224,6 +231,7 @@ body: |
; AVX512F-NEXT: [[ADD:%[0-9]+]]:_(<8 x s64>) = G_ADD [[DEF]], [[DEF1]]
; AVX512F-NEXT: $zmm0 = COPY [[ADD]](<8 x s64>)
; AVX512F-NEXT: RET 0
+ ;
; AVX512BW-LABEL: name: test_add_v8i64
; AVX512BW: liveins: $zmm0, $zmm1
; AVX512BW-NEXT: {{ $}}
@@ -279,6 +287,7 @@ body: |
; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
; AVX1-NEXT: $ymm1 = COPY [[CONCAT_VECTORS1]](<32 x s8>)
; AVX1-NEXT: RET 0, implicit $ymm0, implicit $ymm1
+ ;
; AVX512F-LABEL: name: test_add_v64i8_2
; AVX512F: liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX512F-NEXT: {{ $}}
@@ -291,6 +300,7 @@ body: |
; AVX512F-NEXT: $ymm0 = COPY [[ADD]](<32 x s8>)
; AVX512F-NEXT: $ymm1 = COPY [[ADD1]](<32 x s8>)
; AVX512F-NEXT: RET 0, implicit $ymm0, implicit $ymm1
+ ;
; AVX512BW-LABEL: name: test_add_v64i8_2
; AVX512BW: liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX512BW-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir
index a595324edbbea2..ec9db781b1bc2b 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
-# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X32
+# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
--- |
@@ -152,15 +152,16 @@ body: |
; X64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY]]
; X64-NEXT: $rax = COPY [[ADD]](s64)
; X64-NEXT: RET 0
- ; X32-LABEL: name: test_add_i42
- ; X32: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
- ; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; X32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; X32-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
- ; X32-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
- ; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
- ; X32-NEXT: $rax = COPY [[MV]](s64)
- ; X32-NEXT: RET 0
+ ;
+ ; X86-LABEL: name: test_add_i42
+ ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
+ ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
%0(s64) = COPY $rdx
%1(s42) = G_TRUNC %0(s64)
%2(s42) = G_ADD %1, %1
@@ -185,16 +186,17 @@ body: |
; X64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[DEF]], [[DEF1]]
; X64-NEXT: $rax = COPY [[ADD]](s64)
; X64-NEXT: RET 0
- ; X32-LABEL: name: test_add_i64
- ; X32: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
- ; X32-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
- ; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
- ; X32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
- ; X32-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
- ; X32-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
- ; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
- ; X32-NEXT: $rax = COPY [[MV]](s64)
- ; X32-NEXT: RET 0
+ ;
+ ; X86-LABEL: name: test_add_i64
+ ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
+ ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
+ ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
%1(s64) = IMPLICIT_DEF
%2(s64) = G_ADD %0, %1
@@ -222,20 +224,21 @@ body: |
; X64-NEXT: $rax = COPY [[UADDO]](s64)
; X64-NEXT: $rdx = COPY [[UADDE]](s64)
; X64-NEXT: RET 0
- ; X32-LABEL: name: test_add_i128
- ; X32: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF
- ; X32-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
- ; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
- ; X32-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
- ; X32-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV4]]
- ; X32-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV5]], [[UADDO1]]
- ; X32-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV6]], [[UADDE1]]
- ; X32-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV7]], [[UADDE3]]
- ; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
- ; X32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE2]](s32), [[UADDE4]](s32)
- ; X32-NEXT: $rax = COPY [[MV]](s64)
- ; X32-NEXT: $rdx = COPY [[MV1]](s64)
- ; X32-NEXT: RET 0
+ ;
+ ; X86-LABEL: name: test_add_i128
+ ; X86: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF
+ ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
+ ; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
+ ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV4]]
+ ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV5]], [[UADDO1]]
+ ; X86-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV6]], [[UADDE1]]
+ ; X86-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV7]], [[UADDE3]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
+ ; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE2]](s32), [[UADDE4]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: $rdx = COPY [[MV1]](s64)
+ ; X86-NEXT: RET 0
%0(s128) = IMPLICIT_DEF
%1(s128) = IMPLICIT_DEF
%2(s128) = G_ADD %0, %1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
index c11522faa41f52..76d2a4c954f18f 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
@@ -52,6 +52,7 @@ body: |
; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[SUB]](<16 x s8>), [[SUB1]](<16 x s8>)
; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
; SSE2-NEXT: RET 0
+ ;
; AVX1-LABEL: name: test_sub_v32i8
; AVX1: liveins: $ymm0, $ymm1
; AVX1-NEXT: {{ $}}
@@ -64,6 +65,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[SUB]](<16 x s8>), [[SUB1]](<16 x s8>)
; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
; AVX1-NEXT: RET 0
+ ;
; AVX2-LABEL: name: test_sub_v32i8
; AVX2: liveins: $ymm0, $ymm1
; AVX2-NEXT: {{ $}}
@@ -104,6 +106,7 @@ body: |
; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[SUB]](<8 x s16>), [[SUB1]](<8 x s16>)
; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
; SSE2-NEXT: RET 0
+ ;
; AVX1-LABEL: name: test_sub_v16i16
; AVX1: liveins: $ymm0, $ymm1
; AVX1-NEXT: {{ $}}
@@ -116,6 +119,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[SUB]](<8 x s16>), [[SUB1]](<8 x s16>)
; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
; AVX1-NEXT: RET 0
+ ;
; AVX2-LABEL: name: test_sub_v16i16
; AVX2: liveins: $ymm0, $ymm1
; AVX2-NEXT: {{ $}}
@@ -156,6 +160,7 @@ body: |
; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[SUB]](<4 x s32>), [[SUB1]](<4 x s32>)
; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
; SSE2-NEXT: RET 0
+ ;
; AVX1-LABEL: name: test_sub_v8i32
; AVX1: liveins: $ymm0, $ymm1
; AVX1-NEXT: {{ $}}
@@ -168,6 +173,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[SUB]](<4 x s32>), [[SUB1]](<4 x s32>)
; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
; AVX1-NEXT: RET 0
+ ;
; AVX2-LABEL: name: test_sub_v8i32
; AVX2: liveins: $ymm0, $ymm1
; AVX2-NEXT: {{ $}}
@@ -208,6 +214,7 @@ body: |
; SSE2-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[SUB]](<2 x s64>), [[SUB1]](<2 x s64>)
; SSE2-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
; SSE2-NEXT: RET 0
+ ;
; AVX1-LABEL: name: test_sub_v4i64
; AVX1: liveins: $ymm0, $ymm1
; AVX1-NEXT: {{ $}}
@@ -220,6 +227,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[SUB]](<2 x s64>), [[SUB1]](<2 x s64>)
; AVX1-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
; AVX1-NEXT: RET 0
+ ;
; AVX2-LABEL: name: test_sub_v4i64
; AVX2: liveins: $ymm0, $ymm1
; AVX2-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
index 1c0448990f1f17..c83664bc1ec083 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
@@ -54,6 +54,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[SUB]](<16 x s8>), [[SUB1]](<16 x s8>), [[SUB2]](<16 x s8>), [[SUB3]](<16 x s8>)
; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
; AVX1-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_sub_v64i8
; AVX512F: liveins: $zmm0, $zmm1
; AVX512F-NEXT: {{ $}}
@@ -66,6 +67,7 @@ body: |
; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[SUB]](<32 x s8>), [[SUB1]](<32 x s8>)
; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
; AVX512F-NEXT: RET 0
+ ;
; AVX512BW-LABEL: name: test_sub_v64i8
; AVX512BW: liveins: $zmm0, $zmm1
; AVX512BW-NEXT: {{ $}}
@@ -108,6 +110,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[SUB]](<8 x s16>), [[SUB1]](<8 x s16>), [[SUB2]](<8 x s16>), [[SUB3]](<8 x s16>)
; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
; AVX1-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_sub_v32i16
; AVX512F: liveins: $zmm0, $zmm1
; AVX512F-NEXT: {{ $}}
@@ -120,6 +123,7 @@ body: |
; AVX512F-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[SUB]](<16 x s16>), [[SUB1]](<16 x s16>)
; AVX512F-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
; AVX512F-NEXT: RET 0
+ ;
; AVX512BW-LABEL: name: test_sub_v32i16
; AVX512BW: liveins: $zmm0, $zmm1
; AVX512BW-NEXT: {{ $}}
@@ -162,6 +166,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[SUB]](<4 x s32>), [[SUB1]](<4 x s32>), [[SUB2]](<4 x s32>), [[SUB3]](<4 x s32>)
; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
; AVX1-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_sub_v16i32
; AVX512F: liveins: $zmm0, $zmm1
; AVX512F-NEXT: {{ $}}
@@ -170,6 +175,7 @@ body: |
; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
; AVX512F-NEXT: $zmm0 = COPY [[SUB]](<16 x s32>)
; AVX512F-NEXT: RET 0
+ ;
; AVX512BW-LABEL: name: test_sub_v16i32
; AVX512BW: liveins: $zmm0, $zmm1
; AVX512BW-NEXT: {{ $}}
@@ -212,6 +218,7 @@ body: |
; AVX1-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[SUB]](<2 x s64>), [[SUB1]](<2 x s64>), [[SUB2]](<2 x s64>), [[SUB3]](<2 x s64>)
; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
; AVX1-NEXT: RET 0
+ ;
; AVX512F-LABEL: name: test_sub_v8i64
; AVX512F: liveins: $zmm0, $zmm1
; AVX512F-NEXT: {{ $}}
@@ -220,6 +227,7 @@ body: |
; AVX512F-NEXT: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
; AVX512F-NEXT: $zmm0 = COPY [[SUB]](<8 x s64>)
; AVX512F-NEXT: RET 0
+ ;
; AVX512BW-LABEL: name: test_sub_v8i64
; AVX512BW: liveins: $zmm0, $zmm1
; AVX512BW-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
index ce45ed7407fd28..ee2b9eefcb01a9 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
-# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X32
+# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
--- |
@@ -152,15 +152,16 @@ body: |
; X64-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY]]
; X64-NEXT: $rax = COPY [[SUB]](s64)
; X64-NEXT: RET 0
- ; X32-LABEL: name: test_sub_i42
- ; X32: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
- ; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; X32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
- ; X32-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
- ; X32-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
- ; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
- ; X32-NEXT: $rax = COPY [[MV]](s64)
- ; X32-NEXT: RET 0
+ ;
+ ; X86-LABEL: name: test_sub_i42
+ ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
+ ; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
%0(s64) = COPY $rdx
%1(s42) = G_TRUNC %0(s64)
%2(s42) = G_SUB %1, %1
@@ -185,16 +186,17 @@ body: |
; X64-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[DEF]], [[DEF1]]
; X64-NEXT: $rax = COPY [[SUB]](s64)
; X64-NEXT: RET 0
- ; X32-LABEL: name: test_sub_i64
- ; X32: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
- ; X32-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
- ; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
- ; X32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
- ; X32-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
- ; X32-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
- ; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
- ; X32-NEXT: $rax = COPY [[MV]](s64)
- ; X32-NEXT: RET 0
+ ;
+ ; X86-LABEL: name: test_sub_i64
+ ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
+ ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
+ ; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
+ ; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
%1(s64) = IMPLICIT_DEF
%2(s64) = G_SUB %0, %1
@@ -222,20 +224,21 @@ body: |
; X64-NEXT: $rax = COPY [[USUBO]](s64)
; X64-NEXT: $rdx = COPY [[USUBE]](s64)
; X64-NEXT: RET 0
- ; X32-LABEL: name: test_sub_i128
- ; X32: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF
- ; X32-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
- ; X32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
- ; X32-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
- ; X32-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV4]]
- ; X32-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV5]], [[USUBO1]]
- ; X32-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV2]], [[UV6]], [[USUBE1]]
- ; X32-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[UV3]], [[UV7]], [[USUBE3]]
- ; X32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
- ; X32-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBE2]](s32), [[USUBE4]](s32)
- ; X32-NEXT: $rax = COPY [[MV]](s64)
- ; X32-NEXT: $rdx = COPY [[MV1]](s64)
- ; X32-NEXT: RET 0
+ ;
+ ; X86-LABEL: name: test_sub_i128
+ ; X86: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF
+ ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
+ ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
+ ; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
+ ; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV4]]
+ ; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV5]], [[USUBO1]]
+ ; X86-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV2]], [[UV6]], [[USUBE1]]
+ ; X86-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[UV3]], [[UV7]], [[USUBE3]]
+ ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
+ ; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBE2]](s32), [[USUBE4]](s32)
+ ; X86-NEXT: $rax = COPY [[MV]](s64)
+ ; X86-NEXT: $rdx = COPY [[MV1]](s64)
+ ; X86-NEXT: RET 0
%0(s128) = IMPLICIT_DEF
%1(s128) = IMPLICIT_DEF
%2(s128) = G_SUB %0, %1
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