[llvm] 619c6c0 - [RISCV][test] Add RV32I and RV64I RUN lines to llvm.frexp.ll
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 6 05:36:14 PDT 2023
Author: Alex Bradbury
Date: 2023-07-06T13:36:03+01:00
New Revision: 619c6c0e38a74c0f0de09bed4542887913db98b8
URL: https://github.com/llvm/llvm-project/commit/619c6c0e38a74c0f0de09bed4542887913db98b8
DIFF: https://github.com/llvm/llvm-project/commit/619c6c0e38a74c0f0de09bed4542887913db98b8.diff
LOG: [RISCV][test] Add RV32I and RV64I RUN lines to llvm.frexp.ll
Thanks to D154555, these intrinsics no longer crash when used with a
soft float ABI.
Added:
Modified:
llvm/test/CodeGen/RISCV/llvm.frexp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/llvm.frexp.ll b/llvm/test/CodeGen/RISCV/llvm.frexp.ll
index 150e4d15a8bc50..f8a8cfc60f14d6 100644
--- a/llvm/test/CodeGen/RISCV/llvm.frexp.ll
+++ b/llvm/test/CodeGen/RISCV/llvm.frexp.ll
@@ -11,8 +11,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+zdinx \
; RUN: -verify-machineinstrs -target-abi=lp64 < %s \
; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s
-
-; TODO: Fix soft float codegen (currently crashes).
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
; TODO: FIXMEs are copied blindly across from the X86 version of this test.
@@ -95,6 +97,28 @@ define { float, i32 } @test_frexp_f32_i32(float %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_f32_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: lw a1, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_f32_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: lw a1, 4(sp)
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
ret { float, i32 } %result
}
@@ -139,6 +163,26 @@ define float @test_frexp_f32_i32_only_use_fract(float %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_f32_i32_only_use_fract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_f32_i32_only_use_fract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
%result.0 = extractvalue { float, i32 } %result, 0
ret float %result.0
@@ -188,6 +232,28 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_f32_i32_only_use_exp:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: lw a0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_f32_i32_only_use_exp:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: lw a0, 4(sp)
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
%result.0 = extractvalue { float, i32 } %result, 1
ret i32 %result.0
@@ -407,6 +473,106 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi
; RV64IZFINXZDINX-NEXT: ld s4, 32(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 80
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_v4f32_v4i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -48
+; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s0, 12(a1)
+; RV32I-NEXT: lw s1, 8(a1)
+; RV32I-NEXT: lw s2, 4(a1)
+; RV32I-NEXT: lw a2, 0(a1)
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: addi a1, sp, 12
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: addi a1, sp, 16
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi a1, sp, 20
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: lw a1, 8(sp)
+; RV32I-NEXT: lw a2, 12(sp)
+; RV32I-NEXT: lw a3, 16(sp)
+; RV32I-NEXT: lw a4, 20(sp)
+; RV32I-NEXT: sw a0, 12(s3)
+; RV32I-NEXT: sw s1, 8(s3)
+; RV32I-NEXT: sw s2, 4(s3)
+; RV32I-NEXT: sw s4, 0(s3)
+; RV32I-NEXT: sw a4, 28(s3)
+; RV32I-NEXT: sw a3, 24(s3)
+; RV32I-NEXT: sw a2, 20(s3)
+; RV32I-NEXT: sw a1, 16(s3)
+; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_v4f32_v4i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -64
+; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw s0, 24(a1)
+; RV64I-NEXT: lw s1, 16(a1)
+; RV64I-NEXT: lw s2, 8(a1)
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: mv a1, sp
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: addi a1, sp, 8
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: lw a1, 0(sp)
+; RV64I-NEXT: lw a2, 4(sp)
+; RV64I-NEXT: lw a3, 8(sp)
+; RV64I-NEXT: lw a4, 12(sp)
+; RV64I-NEXT: sw a0, 12(s3)
+; RV64I-NEXT: sw s1, 8(s3)
+; RV64I-NEXT: sw s2, 4(s3)
+; RV64I-NEXT: sw s4, 0(s3)
+; RV64I-NEXT: sw a4, 28(s3)
+; RV64I-NEXT: sw a3, 24(s3)
+; RV64I-NEXT: sw a2, 20(s3)
+; RV64I-NEXT: sw a1, 16(s3)
+; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ret
%result = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> %a)
ret { <4 x float>, <4 x i32> } %result
}
@@ -575,6 +741,90 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi
; RV64IZFINXZDINX-NEXT: ld s4, 32(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 80
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_v4f32_v4i32_only_use_fract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -48
+; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s0, 12(a1)
+; RV32I-NEXT: lw s1, 8(a1)
+; RV32I-NEXT: lw s2, 4(a1)
+; RV32I-NEXT: lw a2, 0(a1)
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: mv s4, a0
+; RV32I-NEXT: addi a1, sp, 12
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: addi a1, sp, 16
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi a1, sp, 20
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: sw a0, 12(s3)
+; RV32I-NEXT: sw s1, 8(s3)
+; RV32I-NEXT: sw s2, 4(s3)
+; RV32I-NEXT: sw s4, 0(s3)
+; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_v4f32_v4i32_only_use_fract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -64
+; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw s0, 24(a1)
+; RV64I-NEXT: lw s1, 16(a1)
+; RV64I-NEXT: lw s2, 8(a1)
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: mv a1, sp
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: mv s4, a0
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: mv s2, a0
+; RV64I-NEXT: addi a1, sp, 8
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: sw a0, 12(s3)
+; RV64I-NEXT: sw s1, 8(s3)
+; RV64I-NEXT: sw s2, 4(s3)
+; RV64I-NEXT: sw s4, 0(s3)
+; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ret
%result = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> %a)
%result.0 = extractvalue { <4 x float>, <4 x i32> } %result, 0
ret <4 x float> %result.0
@@ -740,6 +990,88 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld s3, 40(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 80
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_v4f32_v4i32_only_use_exp:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -48
+; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s0, 12(a1)
+; RV32I-NEXT: lw s1, 8(a1)
+; RV32I-NEXT: lw s2, 4(a1)
+; RV32I-NEXT: lw a2, 0(a1)
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: addi a1, sp, 12
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: addi a1, sp, 16
+; RV32I-NEXT: mv a0, s2
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: addi a1, sp, 20
+; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: addi a1, sp, 24
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: call frexpf at plt
+; RV32I-NEXT: lw a0, 24(sp)
+; RV32I-NEXT: lw a1, 20(sp)
+; RV32I-NEXT: lw a2, 16(sp)
+; RV32I-NEXT: lw a3, 12(sp)
+; RV32I-NEXT: sw a0, 12(s3)
+; RV32I-NEXT: sw a1, 8(s3)
+; RV32I-NEXT: sw a2, 4(s3)
+; RV32I-NEXT: sw a3, 0(s3)
+; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_v4f32_v4i32_only_use_exp:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -64
+; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lw s0, 24(a1)
+; RV64I-NEXT: lw s1, 16(a1)
+; RV64I-NEXT: lw s2, 8(a1)
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: mv s3, a0
+; RV64I-NEXT: addi a1, sp, 8
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: mv a0, s2
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: addi a1, sp, 16
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: addi a1, sp, 20
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call frexpf at plt
+; RV64I-NEXT: lw a0, 20(sp)
+; RV64I-NEXT: lw a1, 16(sp)
+; RV64I-NEXT: lw a2, 12(sp)
+; RV64I-NEXT: lw a3, 8(sp)
+; RV64I-NEXT: sw a0, 12(s3)
+; RV64I-NEXT: sw a1, 8(s3)
+; RV64I-NEXT: sw a2, 4(s3)
+; RV64I-NEXT: sw a3, 0(s3)
+; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 64
+; RV64I-NEXT: ret
%result = call { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float> %a)
%result.1 = extractvalue { <4 x float>, <4 x i32> } %result, 1
ret <4 x i32> %result.1
@@ -789,6 +1121,37 @@ define { double, i32 } @test_frexp_f64_i32(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_f64_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a3, a2
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: addi a2, sp, 4
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: mv a1, a3
+; RV32I-NEXT: call frexp at plt
+; RV32I-NEXT: lw a2, 4(sp)
+; RV32I-NEXT: sw a1, 4(s0)
+; RV32I-NEXT: sw a0, 0(s0)
+; RV32I-NEXT: sw a2, 8(s0)
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_f64_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: call frexp at plt
+; RV64I-NEXT: lw a1, 4(sp)
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
ret { double, i32 } %result
}
@@ -833,6 +1196,26 @@ define double @test_frexp_f64_i32_only_use_fract(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_f64_i32_only_use_fract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a2, sp, 8
+; RV32I-NEXT: call frexp at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_f64_i32_only_use_fract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: call frexp at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
%result.0 = extractvalue { double, i32 } %result, 0
ret double %result.0
@@ -882,6 +1265,28 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_f64_i32_only_use_exp:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: addi a2, sp, 8
+; RV32I-NEXT: call frexp at plt
+; RV32I-NEXT: lw a0, 8(sp)
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_f64_i32_only_use_exp:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: call frexp at plt
+; RV64I-NEXT: lw a0, 4(sp)
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
%result.0 = extractvalue { double, i32 } %result, 1
ret i32 %result.0
@@ -1011,6 +1416,59 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 32
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_f128_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -48
+; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 0(a1)
+; RV32I-NEXT: lw a2, 4(a1)
+; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a1, 12(a1)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: sw a1, 12(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a2, 4(sp)
+; RV32I-NEXT: addi a0, sp, 16
+; RV32I-NEXT: mv a1, sp
+; RV32I-NEXT: addi a2, sp, 36
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: call frexpl at plt
+; RV32I-NEXT: lw a0, 36(sp)
+; RV32I-NEXT: lw a1, 28(sp)
+; RV32I-NEXT: lw a2, 24(sp)
+; RV32I-NEXT: lw a3, 20(sp)
+; RV32I-NEXT: lw a4, 16(sp)
+; RV32I-NEXT: sw a1, 12(s0)
+; RV32I-NEXT: sw a2, 8(s0)
+; RV32I-NEXT: sw a3, 4(s0)
+; RV32I-NEXT: sw a4, 0(s0)
+; RV32I-NEXT: sw a0, 16(s0)
+; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_f128_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv a3, a2
+; RV64I-NEXT: mv s0, a0
+; RV64I-NEXT: addi a2, sp, 12
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: mv a1, a3
+; RV64I-NEXT: call frexpl at plt
+; RV64I-NEXT: lw a2, 12(sp)
+; RV64I-NEXT: sd a1, 8(s0)
+; RV64I-NEXT: sd a0, 0(s0)
+; RV64I-NEXT: sw a2, 16(s0)
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
+; RV64I-NEXT: ret
%result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
ret { fp128, i32 } %result
}
@@ -1097,6 +1555,47 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_f128_i32_only_use_fract:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -48
+; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 0(a1)
+; RV32I-NEXT: lw a2, 4(a1)
+; RV32I-NEXT: lw a4, 8(a1)
+; RV32I-NEXT: lw a1, 12(a1)
+; RV32I-NEXT: mv s0, a0
+; RV32I-NEXT: sw a1, 12(sp)
+; RV32I-NEXT: sw a4, 8(sp)
+; RV32I-NEXT: sw a2, 4(sp)
+; RV32I-NEXT: addi a0, sp, 16
+; RV32I-NEXT: mv a1, sp
+; RV32I-NEXT: addi a2, sp, 36
+; RV32I-NEXT: sw a3, 0(sp)
+; RV32I-NEXT: call frexpl at plt
+; RV32I-NEXT: lw a0, 28(sp)
+; RV32I-NEXT: lw a1, 24(sp)
+; RV32I-NEXT: lw a2, 20(sp)
+; RV32I-NEXT: lw a3, 16(sp)
+; RV32I-NEXT: sw a0, 12(s0)
+; RV32I-NEXT: sw a1, 8(s0)
+; RV32I-NEXT: sw a2, 4(s0)
+; RV32I-NEXT: sw a3, 0(s0)
+; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_f128_i32_only_use_fract:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi a2, sp, 4
+; RV64I-NEXT: call frexpl at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
%result.0 = extractvalue { fp128, i32 } %result, 0
ret fp128 %result.0
@@ -1166,6 +1665,38 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind {
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
+;
+; RV32I-LABEL: test_frexp_f128_i32_only_use_exp:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -48
+; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw a3, 0(a0)
+; RV32I-NEXT: lw a1, 4(a0)
+; RV32I-NEXT: lw a2, 8(a0)
+; RV32I-NEXT: lw a0, 12(a0)
+; RV32I-NEXT: sw a0, 20(sp)
+; RV32I-NEXT: sw a2, 16(sp)
+; RV32I-NEXT: sw a1, 12(sp)
+; RV32I-NEXT: addi a0, sp, 24
+; RV32I-NEXT: addi a1, sp, 8
+; RV32I-NEXT: addi a2, sp, 40
+; RV32I-NEXT: sw a3, 8(sp)
+; RV32I-NEXT: call frexpl at plt
+; RV32I-NEXT: lw a0, 40(sp)
+; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 48
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: test_frexp_f128_i32_only_use_exp:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi a2, sp, 4
+; RV64I-NEXT: call frexpl at plt
+; RV64I-NEXT: lw a0, 4(sp)
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
%result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
%result.0 = extractvalue { fp128, i32 } %result, 1
ret i32 %result.0
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