[PATCH] D153842: [PowerPC] Update input operands information of Power10 scheduling model

[ChenZheng via Phabricator via llvm-commits]

shchenz added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/P10InstrResources.td:317
+    BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL,
+    BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR,
+    BCLRL, BCLRLn, BDNZLRL, BDNZLRLm, BDNZLRLp, BDZLRL, BDZLRLm, BDZLRLp, gBCLRL,
----------------
I am not familiar with the syntax here. But seems from the td file:
```
   def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
                             "bdnzlr", IIC_BrB, []>;
```

BDNZLR should have 0 input operands. But after the change, we now treat it as 1 input operand. Do you know why?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D153842/new/

https://reviews.llvm.org/D153842