[llvm] a813a63 - [RISCV][NFC] Use common prefix to simlify test.
Jianjian GUAN via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 5 20:52:58 PDT 2023
Author: Jianjian GUAN
Date: 2023-07-06T11:52:51+08:00
New Revision: a813a633d54ed1bd2a2fbaa9bb1e5e2954a78c80
URL: https://github.com/llvm/llvm-project/commit/a813a633d54ed1bd2a2fbaa9bb1e5e2954a78c80
DIFF: https://github.com/llvm/llvm-project/commit/a813a633d54ed1bd2a2fbaa9bb1e5e2954a78c80.diff
LOG: [RISCV][NFC] Use common prefix to simlify test.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D154487
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
index c8ff6b425bb5f3..f511145fa0ed99 100644
--- a/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | \
-; RUN: FileCheck %s -check-prefix=RV32
+; RUN: FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | \
-; RUN: FileCheck %s -check-prefix=RV64
+; RUN: FileCheck %s
; ================================================================================
; trunc <vscale x 1 x half>
@@ -11,184 +11,112 @@
declare <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half>)
define <vscale x 1 x i8> @trunc_nxv1f16_to_si8(<vscale x 1 x half> %x) {
-; RV32-LABEL: trunc_nxv1f16_to_si8:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv1f16_to_si8:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV64-NEXT: vfncvt.rtz.x.f.w v9, v8
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv1f16_to_si8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
%b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i8>
ret <vscale x 1 x i8> %b
}
define <vscale x 1 x i8> @trunc_nxv1f16_to_ui8(<vscale x 1 x half> %x) {
-; RV32-LABEL: trunc_nxv1f16_to_ui8:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv1f16_to_ui8:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv1f16_to_ui8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
%b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i8>
ret <vscale x 1 x i8> %b
}
define <vscale x 1 x i16> @trunc_nxv1f16_to_si16(<vscale x 1 x half> %x) {
-; RV32-LABEL: trunc_nxv1f16_to_si16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfcvt.rtz.x.f.v v8, v8
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv1f16_to_si16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfcvt.rtz.x.f.v v8, v8
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv1f16_to_si16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
%b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i16>
ret <vscale x 1 x i16> %b
}
define <vscale x 1 x i16> @trunc_nxv1f16_to_ui16(<vscale x 1 x half> %x) {
-; RV32-LABEL: trunc_nxv1f16_to_ui16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv1f16_to_ui16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv1f16_to_ui16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
%b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i16>
ret <vscale x 1 x i16> %b
}
define <vscale x 1 x i32> @trunc_nxv1f16_to_si32(<vscale x 1 x half> %x) {
-; RV32-LABEL: trunc_nxv1f16_to_si32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfwcvt.rtz.x.f.v v9, v8
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv1f16_to_si32:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfwcvt.rtz.x.f.v v9, v8
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv1f16_to_si32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
%b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i32>
ret <vscale x 1 x i32> %b
}
define <vscale x 1 x i32> @trunc_nxv1f16_to_ui32(<vscale x 1 x half> %x) {
-; RV32-LABEL: trunc_nxv1f16_to_ui32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfwcvt.rtz.xu.f.v v9, v8
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv1f16_to_ui32:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfwcvt.rtz.xu.f.v v9, v8
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv1f16_to_ui32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
%b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i32>
ret <vscale x 1 x i32> %b
}
define <vscale x 1 x i64> @trunc_nxv1f16_to_si64(<vscale x 1 x half> %x) {
-; RV32-LABEL: trunc_nxv1f16_to_si64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, %hi(.LCPI6_0)
-; RV32-NEXT: flh fa5, %lo(.LCPI6_0)(a0)
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
-; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV32-NEXT: vfwcvt.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv1f16_to_si64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, %hi(.LCPI6_0)
-; RV64-NEXT: flh fa5, %lo(.LCPI6_0)(a0)
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfabs.v v9, v8
-; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
-; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV64-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv1f16_to_si64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI6_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
+; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
%b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i64>
ret <vscale x 1 x i64> %b
}
define <vscale x 1 x i64> @trunc_nxv1f16_to_ui64(<vscale x 1 x half> %x) {
-; RV32-LABEL: trunc_nxv1f16_to_ui64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, %hi(.LCPI7_0)
-; RV32-NEXT: flh fa5, %lo(.LCPI7_0)(a0)
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
-; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV32-NEXT: vfwcvt.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv1f16_to_ui64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, %hi(.LCPI7_0)
-; RV64-NEXT: flh fa5, %lo(.LCPI7_0)(a0)
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfabs.v v9, v8
-; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
-; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV64-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv1f16_to_ui64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI7_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
+; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.trunc.nxv1f16(<vscale x 1 x half> %x)
%b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i64>
ret <vscale x 1 x i64> %b
@@ -201,184 +129,112 @@ define <vscale x 1 x i64> @trunc_nxv1f16_to_ui64(<vscale x 1 x half> %x) {
declare <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half>)
define <vscale x 4 x i8> @trunc_nxv4f16_to_si8(<vscale x 4 x half> %x) {
-; RV32-LABEL: trunc_nxv4f16_to_si8:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv4f16_to_si8:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV64-NEXT: vfncvt.rtz.x.f.w v9, v8
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv4f16_to_si8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
%b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i8>
ret <vscale x 4 x i8> %b
}
define <vscale x 4 x i8> @trunc_nxv4f16_to_ui8(<vscale x 4 x half> %x) {
-; RV32-LABEL: trunc_nxv4f16_to_ui8:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV32-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv4f16_to_ui8:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV64-NEXT: vfncvt.rtz.xu.f.w v9, v8
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv4f16_to_ui8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
%b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i8>
ret <vscale x 4 x i8> %b
}
define <vscale x 4 x i16> @trunc_nxv4f16_to_si16(<vscale x 4 x half> %x) {
-; RV32-LABEL: trunc_nxv4f16_to_si16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vfcvt.rtz.x.f.v v8, v8
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv4f16_to_si16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vfcvt.rtz.x.f.v v8, v8
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv4f16_to_si16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
%b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>
ret <vscale x 4 x i16> %b
}
define <vscale x 4 x i16> @trunc_nxv4f16_to_ui16(<vscale x 4 x half> %x) {
-; RV32-LABEL: trunc_nxv4f16_to_ui16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv4f16_to_ui16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv4f16_to_ui16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
%b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>
ret <vscale x 4 x i16> %b
}
define <vscale x 4 x i32> @trunc_nxv4f16_to_si32(<vscale x 4 x half> %x) {
-; RV32-LABEL: trunc_nxv4f16_to_si32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vfwcvt.rtz.x.f.v v10, v8
-; RV32-NEXT: vmv2r.v v8, v10
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv4f16_to_si32:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vfwcvt.rtz.x.f.v v10, v8
-; RV64-NEXT: vmv2r.v v8, v10
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv4f16_to_si32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
%b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>
ret <vscale x 4 x i32> %b
}
define <vscale x 4 x i32> @trunc_nxv4f16_to_ui32(<vscale x 4 x half> %x) {
-; RV32-LABEL: trunc_nxv4f16_to_ui32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vfwcvt.rtz.xu.f.v v10, v8
-; RV32-NEXT: vmv2r.v v8, v10
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv4f16_to_ui32:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vfwcvt.rtz.xu.f.v v10, v8
-; RV64-NEXT: vmv2r.v v8, v10
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv4f16_to_ui32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
%b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>
ret <vscale x 4 x i32> %b
}
define <vscale x 4 x i64> @trunc_nxv4f16_to_si64(<vscale x 4 x half> %x) {
-; RV32-LABEL: trunc_nxv4f16_to_si64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, %hi(.LCPI14_0)
-; RV32-NEXT: flh fa5, %lo(.LCPI14_0)(a0)
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
-; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV32-NEXT: vfwcvt.f.f.v v12, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v12
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv4f16_to_si64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, %hi(.LCPI14_0)
-; RV64-NEXT: flh fa5, %lo(.LCPI14_0)(a0)
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vfabs.v v9, v8
-; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
-; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV64-NEXT: vfwcvt.f.f.v v12, v8
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v12
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv4f16_to_si64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI14_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
+; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
%b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i64>
ret <vscale x 4 x i64> %b
}
define <vscale x 4 x i64> @trunc_nxv4f16_to_ui64(<vscale x 4 x half> %x) {
-; RV32-LABEL: trunc_nxv4f16_to_ui64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, %hi(.LCPI15_0)
-; RV32-NEXT: flh fa5, %lo(.LCPI15_0)(a0)
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
-; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV32-NEXT: vfwcvt.f.f.v v12, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v12
-; RV32-NEXT: ret
-;
-; RV64-LABEL: trunc_nxv4f16_to_ui64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, %hi(.LCPI15_0)
-; RV64-NEXT: flh fa5, %lo(.LCPI15_0)(a0)
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vfabs.v v9, v8
-; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
-; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV64-NEXT: vfwcvt.f.f.v v12, v8
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v12
-; RV64-NEXT: ret
+; CHECK-LABEL: trunc_nxv4f16_to_ui64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI15_0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI15_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
+; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.trunc.nxv4f16(<vscale x 4 x half> %x)
%b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i64>
ret <vscale x 4 x i64> %b
@@ -391,216 +247,128 @@ define <vscale x 4 x i64> @trunc_nxv4f16_to_ui64(<vscale x 4 x half> %x) {
declare <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half>)
define <vscale x 1 x i8> @ceil_nxv1f16_to_si8(<vscale x 1 x half> %x) {
-; RV32-LABEL: ceil_nxv1f16_to_si8:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v9, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv1f16_to_si8:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; RV64-NEXT: vfncvt.x.f.w v9, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv1f16_to_si8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
%b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i8>
ret <vscale x 1 x i8> %b
}
define <vscale x 1 x i8> @ceil_nxv1f16_to_ui8(<vscale x 1 x half> %x) {
-; RV32-LABEL: ceil_nxv1f16_to_ui8:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; RV32-NEXT: vfncvt.xu.f.w v9, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv1f16_to_ui8:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; RV64-NEXT: vfncvt.xu.f.w v9, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv1f16_to_ui8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
%b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i8>
ret <vscale x 1 x i8> %b
}
define <vscale x 1 x i16> @ceil_nxv1f16_to_si16(<vscale x 1 x half> %x) {
-; RV32-LABEL: ceil_nxv1f16_to_si16:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv1f16_to_si16:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfcvt.x.f.v v8, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv1f16_to_si16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
%b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i16>
ret <vscale x 1 x i16> %b
}
define <vscale x 1 x i16> @ceil_nxv1f16_to_ui16(<vscale x 1 x half> %x) {
-; RV32-LABEL: ceil_nxv1f16_to_ui16:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfcvt.xu.f.v v8, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv1f16_to_ui16:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfcvt.xu.f.v v8, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv1f16_to_ui16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfcvt.xu.f.v v8, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
%b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i16>
ret <vscale x 1 x i16> %b
}
define <vscale x 1 x i32> @ceil_nxv1f16_to_si32(<vscale x 1 x half> %x) {
-; RV32-LABEL: ceil_nxv1f16_to_si32:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfwcvt.x.f.v v9, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv1f16_to_si32:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfwcvt.x.f.v v9, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv1f16_to_si32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.x.f.v v9, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
%b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i32>
ret <vscale x 1 x i32> %b
}
define <vscale x 1 x i32> @ceil_nxv1f16_to_ui32(<vscale x 1 x half> %x) {
-; RV32-LABEL: ceil_nxv1f16_to_ui32:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfwcvt.xu.f.v v9, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv1f16_to_ui32:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfwcvt.xu.f.v v9, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv1f16_to_ui32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
%b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i32>
ret <vscale x 1 x i32> %b
}
define <vscale x 1 x i64> @ceil_nxv1f16_to_si64(<vscale x 1 x half> %x) {
-; RV32-LABEL: ceil_nxv1f16_to_si64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, %hi(.LCPI22_0)
-; RV32-NEXT: flh fa5, %lo(.LCPI22_0)(a0)
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV32-NEXT: vfwcvt.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv1f16_to_si64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, %hi(.LCPI22_0)
-; RV64-NEXT: flh fa5, %lo(.LCPI22_0)(a0)
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfabs.v v9, v8
-; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV64-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv1f16_to_si64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI22_0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI22_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
%b = fptosi <vscale x 1 x half> %a to <vscale x 1 x i64>
ret <vscale x 1 x i64> %b
}
define <vscale x 1 x i64> @ceil_nxv1f16_to_ui64(<vscale x 1 x half> %x) {
-; RV32-LABEL: ceil_nxv1f16_to_ui64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, %hi(.LCPI23_0)
-; RV32-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV32-NEXT: vfwcvt.f.f.v v9, v8
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv1f16_to_ui64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, %hi(.LCPI23_0)
-; RV64-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vfabs.v v9, v8
-; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV64-NEXT: vfwcvt.f.f.v v9, v8
-; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv1f16_to_ui64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI23_0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
%b = fptoui <vscale x 1 x half> %a to <vscale x 1 x i64>
ret <vscale x 1 x i64> %b
@@ -613,216 +381,128 @@ define <vscale x 1 x i64> @ceil_nxv1f16_to_ui64(<vscale x 1 x half> %x) {
declare <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half>)
define <vscale x 4 x i8> @ceil_nxv4f16_to_si8(<vscale x 4 x half> %x) {
-; RV32-LABEL: ceil_nxv4f16_to_si8:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV32-NEXT: vfncvt.x.f.w v9, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv4f16_to_si8:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV64-NEXT: vfncvt.x.f.w v9, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv4f16_to_si8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vfncvt.x.f.w v9, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
%b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i8>
ret <vscale x 4 x i8> %b
}
define <vscale x 4 x i8> @ceil_nxv4f16_to_ui8(<vscale x 4 x half> %x) {
-; RV32-LABEL: ceil_nxv4f16_to_ui8:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV32-NEXT: vfncvt.xu.f.w v9, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vmv1r.v v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv4f16_to_ui8:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV64-NEXT: vfncvt.xu.f.w v9, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vmv1r.v v8, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv4f16_to_ui8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vfncvt.xu.f.w v9, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
%b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i8>
ret <vscale x 4 x i8> %b
}
define <vscale x 4 x i16> @ceil_nxv4f16_to_si16(<vscale x 4 x half> %x) {
-; RV32-LABEL: ceil_nxv4f16_to_si16:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV32-NEXT: vfcvt.x.f.v v8, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv4f16_to_si16:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV64-NEXT: vfcvt.x.f.v v8, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv4f16_to_si16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
%b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i16>
ret <vscale x 4 x i16> %b
}
define <vscale x 4 x i16> @ceil_nxv4f16_to_ui16(<vscale x 4 x half> %x) {
-; RV32-LABEL: ceil_nxv4f16_to_ui16:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV32-NEXT: vfcvt.xu.f.v v8, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv4f16_to_ui16:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV64-NEXT: vfcvt.xu.f.v v8, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv4f16_to_ui16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfcvt.xu.f.v v8, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
%b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i16>
ret <vscale x 4 x i16> %b
}
define <vscale x 4 x i32> @ceil_nxv4f16_to_si32(<vscale x 4 x half> %x) {
-; RV32-LABEL: ceil_nxv4f16_to_si32:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV32-NEXT: vfwcvt.x.f.v v10, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vmv2r.v v8, v10
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv4f16_to_si32:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV64-NEXT: vfwcvt.x.f.v v10, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vmv2r.v v8, v10
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv4f16_to_si32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvt.x.f.v v10, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
%b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i32>
ret <vscale x 4 x i32> %b
}
define <vscale x 4 x i32> @ceil_nxv4f16_to_ui32(<vscale x 4 x half> %x) {
-; RV32-LABEL: ceil_nxv4f16_to_ui32:
-; RV32: # %bb.0:
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV32-NEXT: vfwcvt.xu.f.v v10, v8
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vmv2r.v v8, v10
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv4f16_to_ui32:
-; RV64: # %bb.0:
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; RV64-NEXT: vfwcvt.xu.f.v v10, v8
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vmv2r.v v8, v10
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv4f16_to_ui32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvt.xu.f.v v10, v8
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
%b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i32>
ret <vscale x 4 x i32> %b
}
define <vscale x 4 x i64> @ceil_nxv4f16_to_si64(<vscale x 4 x half> %x) {
-; RV32-LABEL: ceil_nxv4f16_to_si64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, %hi(.LCPI30_0)
-; RV32-NEXT: flh fa5, %lo(.LCPI30_0)(a0)
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV32-NEXT: vfwcvt.f.f.v v12, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v12
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv4f16_to_si64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, %hi(.LCPI30_0)
-; RV64-NEXT: flh fa5, %lo(.LCPI30_0)(a0)
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vfabs.v v9, v8
-; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV64-NEXT: vfwcvt.f.f.v v12, v8
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v12
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv4f16_to_si64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI30_0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI30_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
%b = fptosi <vscale x 4 x half> %a to <vscale x 4 x i64>
ret <vscale x 4 x i64> %b
}
define <vscale x 4 x i64> @ceil_nxv4f16_to_ui64(<vscale x 4 x half> %x) {
-; RV32-LABEL: ceil_nxv4f16_to_ui64:
-; RV32: # %bb.0:
-; RV32-NEXT: lui a0, %hi(.LCPI31_0)
-; RV32-NEXT: flh fa5, %lo(.LCPI31_0)(a0)
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
-; RV32-NEXT: fsrm a0
-; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV32-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV32-NEXT: vfwcvt.f.f.v v12, v8
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v12
-; RV32-NEXT: ret
-;
-; RV64-LABEL: ceil_nxv4f16_to_ui64:
-; RV64: # %bb.0:
-; RV64-NEXT: lui a0, %hi(.LCPI31_0)
-; RV64-NEXT: flh fa5, %lo(.LCPI31_0)(a0)
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vfabs.v v9, v8
-; RV64-NEXT: vmflt.vf v0, v9, fa5
-; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
-; RV64-NEXT: fsrm a0
-; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
-; RV64-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
-; RV64-NEXT: vfwcvt.f.f.v v12, v8
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v12
-; RV64-NEXT: ret
+; CHECK-LABEL: ceil_nxv4f16_to_ui64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI31_0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI31_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
+; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
+; CHECK-NEXT: fsrm a0
+; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfwcvt.f.f.v v12, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12
+; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
%b = fptoui <vscale x 4 x half> %a to <vscale x 4 x i64>
ret <vscale x 4 x i64> %b
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