[llvm] 9c4aa85 - [RISCV][TableGen] Remove f32 from XLenFVT for RV32.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-05T17:17:22-07:00
New Revision: 9c4aa85ec18833a25141d1563f579ef9099d6eb9

URL: https://github.com/llvm/llvm-project/commit/9c4aa85ec18833a25141d1563f579ef9099d6eb9
DIFF: https://github.com/llvm/llvm-project/commit/9c4aa85ec18833a25141d1563f579ef9099d6eb9.diff

LOG: [RISCV][TableGen] Remove f32 from XLenFVT for RV32.

We don't expect this to be used on RV32 currently so remove it
to reduce number of entries in the isel table.

Teach RegisterInfoEmitter.cpp to allow a type to be missing for
a particular HwMode.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    llvm/utils/TableGen/RegisterInfoEmitter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 9f7d035640281f..fe29575d255dde 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -115,9 +115,9 @@ let RegAltNameIndices = [ABIRegAltName] in {
 
 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
                                [i32,  i64]>;
-// Floating point class with XLen bits.
-def XLenFVT : ValueTypeByHwMode<[RV32, RV64],
-                                [f32,  f64]>;
+// Allow f64 in GPR for ZDINX on RV64.
+def XLenFVT : ValueTypeByHwMode<[RV64],
+                                [f64]>;
 def XLenRI : RegInfoByHwMode<
       [RV32,              RV64],
       [RegInfo<32,32,32>, RegInfo<64,64,64>]>;

diff  --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 1f433c01dca5f0..3101081114fb31 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1242,7 +1242,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
     for (const auto &RC : RegisterClasses) {
       std::vector<MVT::SimpleValueType> S;
       for (const ValueTypeByHwMode &VVT : RC.VTs)
-        S.push_back(VVT.get(M).SimpleTy);
+        if (VVT.hasDefault() || VVT.hasMode(M))
+          S.push_back(VVT.get(M).SimpleTy);
       VTSeqs.add(S);
     }
   }
@@ -1292,7 +1293,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
            << RI.SpillAlignment;
         std::vector<MVT::SimpleValueType> VTs;
         for (const ValueTypeByHwMode &VVT : RC.VTs)
-          VTs.push_back(VVT.get(M).SimpleTy);
+          if (VVT.hasDefault() || VVT.hasMode(M))
+            VTs.push_back(VVT.get(M).SimpleTy);
         OS << ", VTLists+" << VTSeqs.get(VTs) << " },    // "
            << RC.getName() << '\n';
       }