[PATCH] D138809: [RISCV] Support vector crypto extension LLVM IR
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 5 16:13:19 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:1697
+let TargetPrefix = "riscv" in {
+ // zvbb
+ defm vandn : RISCVBinaryAAX;
----------------
Capitalize the Z in extension names in comments.
================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:1722
+ defm vaesem : RISCVUnaryAAUnMaskedP;
+ def int_riscv_vaeskf1 : RISCVBinaryAAXUnMasked;
+ def int_riscv_vaeskf2 : RISCVBinaryAAXUnMaskedP;
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I think vaeskf1 needs something like `ImmArg<ArgIndex<X>>` for the immediate.
Same for any other instruction with constant arguments.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138809/new/
https://reviews.llvm.org/D138809
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