[PATCH] D153129: [AArch64][RCPC3] Instruction selection for LDAP1/STL1 instructions

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.

LGTM

Not implementing optimized lowering for "double" and SVE seems fine for now, but you might want to consider it for the future.



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Comment at: llvm/test/CodeGen/AArch64/rcpc3.ll:247
+; BOTH-NEXT:    ret
+  %1 = load <2 x i32>, ptr %a, align 8
+  ret <2 x i32> %1
----------------
The tests for a non-atomic load of a vector don't seem necessary.  (I forgot you can't do an atomic load of a vector.)

Maybe worth testing "load atomic i64" followed by a bitcast to <2 x i32>, instead.


Repository:
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https://reviews.llvm.org/D153129