[llvm] 872276d - [NFC] Autogenerate CodeGen/SystemZ/int-{uadd, sub}-0*.ll
Amaury Séchet via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 5 13:15:28 PDT 2023
Author: Amaury Séchet
Date: 2023-07-05T20:14:43Z
New Revision: 872276de4b8c5f13f106b79c53a27e4a6ff8ce35
URL: https://github.com/llvm/llvm-project/commit/872276de4b8c5f13f106b79c53a27e4a6ff8ce35
DIFF: https://github.com/llvm/llvm-project/commit/872276de4b8c5f13f106b79c53a27e4a6ff8ce35.diff
LOG: [NFC] Autogenerate CodeGen/SystemZ/int-{uadd,sub}-0*.ll
Added:
Modified:
llvm/test/CodeGen/SystemZ/int-uadd-01.ll
llvm/test/CodeGen/SystemZ/int-uadd-02.ll
llvm/test/CodeGen/SystemZ/int-uadd-03.ll
llvm/test/CodeGen/SystemZ/int-uadd-04.ll
llvm/test/CodeGen/SystemZ/int-uadd-05.ll
llvm/test/CodeGen/SystemZ/int-uadd-06.ll
llvm/test/CodeGen/SystemZ/int-uadd-07.ll
llvm/test/CodeGen/SystemZ/int-uadd-08.ll
llvm/test/CodeGen/SystemZ/int-uadd-09.ll
llvm/test/CodeGen/SystemZ/int-usub-01.ll
llvm/test/CodeGen/SystemZ/int-usub-02.ll
llvm/test/CodeGen/SystemZ/int-usub-03.ll
llvm/test/CodeGen/SystemZ/int-usub-04.ll
llvm/test/CodeGen/SystemZ/int-usub-05.ll
llvm/test/CodeGen/SystemZ/int-usub-06.ll
llvm/test/CodeGen/SystemZ/int-usub-07.ll
llvm/test/CodeGen/SystemZ/int-usub-08.ll
llvm/test/CodeGen/SystemZ/int-usub-09.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-01.ll b/llvm/test/CodeGen/SystemZ/int-uadd-01.ll
index 30dce9ee2a369a..7d4aa9f3218485 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-01.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 32-bit addition in which the second operand is variable.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,11 +8,12 @@ declare i32 @foo()
; Check ALR.
define zeroext i1 @f1(i32 %dummy, i32 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: alr %r3, %r4
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alr %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -22,10 +24,12 @@ define zeroext i1 @f1(i32 %dummy, i32 %a, i32 %b, ptr %res) {
; Check using the overflow result for a branch.
define void @f2(i32 %dummy, i32 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: alr %r3, %r4
-; CHECK: st %r3, 0(%r5)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alr %r3, %r4
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB1_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -43,10 +47,12 @@ exit:
; ... and the same with the inverted direction.
define void @f3(i32 %dummy, i32 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: alr %r3, %r4
-; CHECK: st %r3, 0(%r5)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alr %r3, %r4
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB2_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -64,11 +70,12 @@ exit:
; Check the low end of the AL range.
define zeroext i1 @f4(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: al %r3, 0(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: al %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%b = load i32, ptr %src
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
@@ -80,11 +87,12 @@ define zeroext i1 @f4(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the high end of the aligned AL range.
define zeroext i1 @f5(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: al %r3, 4092(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: al %r3, 4092(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 1023
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
@@ -97,11 +105,12 @@ define zeroext i1 @f5(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the next word up, which should use ALY instead of AL.
define zeroext i1 @f6(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: aly %r3, 4096(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aly %r3, 4096(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 1024
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
@@ -114,11 +123,12 @@ define zeroext i1 @f6(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the high end of the aligned ALY range.
define zeroext i1 @f7(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: aly %r3, 524284(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aly %r3, 524284(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 131071
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
@@ -132,12 +142,13 @@ define zeroext i1 @f7(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f8(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: agfi %r4, 524288
-; CHECK: al %r3, 0(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, 524288
+; CHECK-NEXT: al %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 131072
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
@@ -150,11 +161,12 @@ define zeroext i1 @f8(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the high end of the negative aligned ALY range.
define zeroext i1 @f9(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f9:
-; CHECK: aly %r3, -4(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aly %r3, -4(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -1
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
@@ -167,11 +179,12 @@ define zeroext i1 @f9(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the low end of the ALY range.
define zeroext i1 @f10(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f10:
-; CHECK: aly %r3, -524288(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aly %r3, -524288(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -131072
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
@@ -185,12 +198,13 @@ define zeroext i1 @f10(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f11(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f11:
-; CHECK: agfi %r4, -524292
-; CHECK: al %r3, 0(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, -524292
+; CHECK-NEXT: al %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -131073
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
@@ -203,11 +217,12 @@ define zeroext i1 @f11(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check that AL allows an index.
define zeroext i1 @f12(i64 %src, i64 %index, i32 %a, ptr %res) {
; CHECK-LABEL: f12:
-; CHECK: al %r4, 4092({{%r3,%r2|%r2,%r3}})
-; CHECK-DAG: st %r4, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: al %r4, 4092(%r3,%r2)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r4, 0(%r5)
+; CHECK-NEXT: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 4092
%ptr = inttoptr i64 %add2 to ptr
@@ -222,11 +237,12 @@ define zeroext i1 @f12(i64 %src, i64 %index, i32 %a, ptr %res) {
; Check that ALY allows an index.
define zeroext i1 @f13(i64 %src, i64 %index, i32 %a, ptr %res) {
; CHECK-LABEL: f13:
-; CHECK: aly %r4, 4096({{%r3,%r2|%r2,%r3}})
-; CHECK-DAG: st %r4, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: aly %r4, 4096(%r3,%r2)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r4, 0(%r5)
+; CHECK-NEXT: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 4096
%ptr = inttoptr i64 %add2 to ptr
@@ -241,9 +257,64 @@ define zeroext i1 @f13(i64 %src, i64 %index, i32 %a, ptr %res) {
; Check that additions of spilled values can use AL rather than ALR.
define zeroext i1 @f14(ptr %ptr0) {
; CHECK-LABEL: f14:
-; CHECK: brasl %r14, foo at PLT
-; CHECK: al %r2, 16{{[04]}}(%r15)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: l %r6, 0(%r2)
+; CHECK-NEXT: l %r13, 8(%r2)
+; CHECK-NEXT: l %r12, 16(%r2)
+; CHECK-NEXT: l %r7, 24(%r2)
+; CHECK-NEXT: l %r8, 32(%r2)
+; CHECK-NEXT: l %r9, 40(%r2)
+; CHECK-NEXT: l %r10, 48(%r2)
+; CHECK-NEXT: l %r11, 56(%r2)
+; CHECK-NEXT: mvc 160(4,%r15), 64(%r2) # 4-byte Folded Spill
+; CHECK-NEXT: mvc 164(4,%r15), 72(%r2) # 4-byte Folded Spill
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: alr %r2, %r6
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r0, %r0, 63, 191, 35
+; CHECK-NEXT: alr %r2, %r13
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: alr %r2, %r12
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: alr %r2, %r7
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: alr %r2, %r8
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: alr %r2, %r9
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: alr %r2, %r10
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: alr %r2, %r11
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: al %r2, 160(%r15) # 4-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: al %r2, 164(%r15) # 4-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 0
+; CHECK-NEXT: lmg %r6, %r15, 216(%r15)
+; CHECK-NEXT: br %r14
%ptr1 = getelementptr i32, ptr %ptr0, i64 2
%ptr2 = getelementptr i32, ptr %ptr0, i64 4
%ptr3 = getelementptr i32, ptr %ptr0, i64 6
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-02.ll b/llvm/test/CodeGen/SystemZ/int-uadd-02.ll
index 8875711254cd8f..46c5b4ff35fc05 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-02.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 64-bit addition in which the second operand is variable.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,11 +8,12 @@ declare i64 @foo()
; Check ALGR.
define zeroext i1 @f1(i64 %dummy, i64 %a, i64 %b, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: algr %r3, %r4
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algr %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -22,10 +24,12 @@ define zeroext i1 @f1(i64 %dummy, i64 %a, i64 %b, ptr %res) {
; Check using the overflow result for a branch.
define void @f2(i64 %dummy, i64 %a, i64 %b, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: algr %r3, %r4
-; CHECK: stg %r3, 0(%r5)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algr %r3, %r4
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB1_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -43,10 +47,12 @@ exit:
; ... and the same with the inverted direction.
define void @f3(i64 %dummy, i64 %a, i64 %b, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: algr %r3, %r4
-; CHECK: stg %r3, 0(%r5)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algr %r3, %r4
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB2_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -64,11 +70,12 @@ exit:
; Check ALG with no displacement.
define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: alg %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alg %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%b = load i64, ptr %src
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
@@ -80,11 +87,12 @@ define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the high end of the aligned ALG range.
define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: alg %r3, 524280(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alg %r3, 524280(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 65535
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
@@ -98,12 +106,13 @@ define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: agfi %r4, 524288
-; CHECK: alg %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, 524288
+; CHECK-NEXT: alg %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 65536
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
@@ -116,11 +125,12 @@ define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the high end of the negative aligned ALG range.
define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: alg %r3, -8(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alg %r3, -8(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 -1
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
@@ -133,11 +143,12 @@ define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the low end of the ALG range.
define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: alg %r3, -524288(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alg %r3, -524288(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 -65536
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
@@ -151,12 +162,13 @@ define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f9:
-; CHECK: agfi %r4, -524296
-; CHECK: alg %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, -524296
+; CHECK-NEXT: alg %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 -65537
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
@@ -169,11 +181,12 @@ define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check that ALG allows an index.
define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {
; CHECK-LABEL: f10:
-; CHECK: alg %r4, 524280({{%r3,%r2|%r2,%r3}})
-; CHECK-DAG: stg %r4, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alg %r4, 524280(%r3,%r2)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r4, 0(%r5)
+; CHECK-NEXT: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524280
%ptr = inttoptr i64 %add2 to ptr
@@ -188,9 +201,64 @@ define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {
; Check that additions of spilled values can use ALG rather than ALGR.
define zeroext i1 @f11(ptr %ptr0) {
; CHECK-LABEL: f11:
-; CHECK: brasl %r14, foo at PLT
-; CHECK: alg %r2, 160(%r15)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lg %r6, 0(%r2)
+; CHECK-NEXT: lg %r13, 16(%r2)
+; CHECK-NEXT: lg %r12, 32(%r2)
+; CHECK-NEXT: lg %r7, 48(%r2)
+; CHECK-NEXT: lg %r8, 64(%r2)
+; CHECK-NEXT: lg %r9, 80(%r2)
+; CHECK-NEXT: lg %r10, 96(%r2)
+; CHECK-NEXT: lg %r11, 112(%r2)
+; CHECK-NEXT: mvc 160(8,%r15), 128(%r2) # 8-byte Folded Spill
+; CHECK-NEXT: mvc 168(8,%r15), 144(%r2) # 8-byte Folded Spill
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: algr %r2, %r6
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r0, %r0, 63, 191, 35
+; CHECK-NEXT: algr %r2, %r13
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algr %r2, %r12
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algr %r2, %r7
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algr %r2, %r8
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algr %r2, %r9
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algr %r2, %r10
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algr %r2, %r11
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: alg %r2, 160(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: alg %r2, 168(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 0
+; CHECK-NEXT: lmg %r6, %r15, 224(%r15)
+; CHECK-NEXT: br %r14
%ptr1 = getelementptr i64, ptr %ptr0, i64 2
%ptr2 = getelementptr i64, ptr %ptr0, i64 4
%ptr3 = getelementptr i64, ptr %ptr0, i64 6
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-03.ll b/llvm/test/CodeGen/SystemZ/int-uadd-03.ll
index 0adce1ad65e08e..4ecbb95b639b1a 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-03.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-03.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test additions between an i64 and a zero-extended i32.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,11 +8,12 @@ declare i64 @foo()
; Check ALGFR.
define zeroext i1 @f1(i64 %dummy, i64 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: algfr %r3, %r4
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algfr %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%bext = zext i32 %b to i64
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
%val = extractvalue {i64, i1} %t, 0
@@ -23,10 +25,12 @@ define zeroext i1 @f1(i64 %dummy, i64 %a, i32 %b, ptr %res) {
; Check using the overflow result for a branch.
define void @f2(i64 %dummy, i64 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: algfr %r3, %r4
-; CHECK: stg %r3, 0(%r5)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algfr %r3, %r4
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB1_1: # %exit
+; CHECK-NEXT: br %r14
%bext = zext i32 %b to i64
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
%val = extractvalue {i64, i1} %t, 0
@@ -45,10 +49,12 @@ exit:
; ... and the same with the inverted direction.
define void @f3(i64 %dummy, i64 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: algfr %r3, %r4
-; CHECK: stg %r3, 0(%r5)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algfr %r3, %r4
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB2_1: # %exit
+; CHECK-NEXT: br %r14
%bext = zext i32 %b to i64
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
%val = extractvalue {i64, i1} %t, 0
@@ -67,11 +73,12 @@ exit:
; Check ALGF with no displacement.
define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: algf %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algf %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%b = load i32, ptr %src
%bext = zext i32 %b to i64
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
@@ -84,11 +91,12 @@ define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the high end of the aligned ALGF range.
define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: algf %r3, 524284(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algf %r3, 524284(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 131071
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -103,12 +111,13 @@ define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: agfi %r4, 524288
-; CHECK: algf %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, 524288
+; CHECK-NEXT: algf %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 131072
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -122,11 +131,12 @@ define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the high end of the negative aligned ALGF range.
define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: algf %r3, -4(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algf %r3, -4(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -1
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -140,11 +150,12 @@ define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the low end of the ALGF range.
define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: algf %r3, -524288(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algf %r3, -524288(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -131072
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -159,12 +170,13 @@ define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f9:
-; CHECK: agfi %r4, -524292
-; CHECK: algf %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, -524292
+; CHECK-NEXT: algf %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -131073
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -178,11 +190,12 @@ define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check that ALGF allows an index.
define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {
; CHECK-LABEL: f10:
-; CHECK: algf %r4, 524284({{%r3,%r2|%r2,%r3}})
-; CHECK-DAG: stg %r4, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algf %r4, 524284(%r3,%r2)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r4, 0(%r5)
+; CHECK-NEXT: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524284
%ptr = inttoptr i64 %add2 to ptr
@@ -198,9 +211,86 @@ define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {
; Check that additions of spilled values can use ALGF rather than ALGFR.
define zeroext i1 @f11(ptr %ptr0) {
; CHECK-LABEL: f11:
-; CHECK: brasl %r14, foo at PLT
-; CHECK: algf {{%r[0-9]+}}, 160(%r15)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: lhi %r0, 100
+; CHECK-NEXT: lhi %r12, 100
+; CHECK-NEXT: a %r12, 0(%r2)
+; CHECK-NEXT: lhi %r13, 100
+; CHECK-NEXT: a %r13, 8(%r2)
+; CHECK-NEXT: lhi %r6, 100
+; CHECK-NEXT: a %r6, 16(%r2)
+; CHECK-NEXT: lhi %r7, 100
+; CHECK-NEXT: a %r7, 24(%r2)
+; CHECK-NEXT: lhi %r8, 100
+; CHECK-NEXT: a %r8, 32(%r2)
+; CHECK-NEXT: lhi %r9, 100
+; CHECK-NEXT: a %r9, 40(%r2)
+; CHECK-NEXT: lhi %r10, 100
+; CHECK-NEXT: a %r10, 48(%r2)
+; CHECK-NEXT: lhi %r11, 100
+; CHECK-NEXT: a %r11, 56(%r2)
+; CHECK-NEXT: lhi %r1, 100
+; CHECK-NEXT: a %r1, 64(%r2)
+; CHECK-NEXT: st %r1, 160(%r15) # 4-byte Folded Spill
+; CHECK-NEXT: a %r0, 72(%r2)
+; CHECK-NEXT: st %r0, 164(%r15) # 4-byte Folded Spill
+; CHECK-NEXT: st %r12, 0(%r2)
+; CHECK-NEXT: st %r13, 8(%r2)
+; CHECK-NEXT: st %r6, 16(%r2)
+; CHECK-NEXT: st %r7, 24(%r2)
+; CHECK-NEXT: st %r8, 32(%r2)
+; CHECK-NEXT: st %r9, 40(%r2)
+; CHECK-NEXT: st %r10, 48(%r2)
+; CHECK-NEXT: st %r11, 56(%r2)
+; CHECK-NEXT: st %r1, 64(%r2)
+; CHECK-NEXT: st %r0, 72(%r2)
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: algfr %r2, %r12
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r0, %r0, 63, 191, 35
+; CHECK-NEXT: algfr %r2, %r13
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algfr %r2, %r6
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algfr %r2, %r7
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algfr %r2, %r8
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algfr %r2, %r9
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algfr %r2, %r10
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algfr %r2, %r11
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algf %r2, 160(%r15) # 4-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: algf %r2, 164(%r15) # 4-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 35
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 0
+; CHECK-NEXT: lmg %r6, %r15, 216(%r15)
+; CHECK-NEXT: br %r14
%ptr1 = getelementptr i32, ptr %ptr0, i64 2
%ptr2 = getelementptr i32, ptr %ptr0, i64 4
%ptr3 = getelementptr i32, ptr %ptr0, i64 6
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-04.ll b/llvm/test/CodeGen/SystemZ/int-uadd-04.ll
index 5b0a58f72783c4..92a3f094ee2753 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-04.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-04.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 32-bit addition in which the second operand is constant.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,11 +8,12 @@ declare i32 @foo()
; Check addition of 1.
define zeroext i1 @f1(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: alfi %r3, 1
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alfi %r3, 1
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -22,11 +24,12 @@ define zeroext i1 @f1(i32 %dummy, i32 %a, ptr %res) {
; Check the high end of the ALFI range.
define zeroext i1 @f2(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: alfi %r3, 4294967295
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alfi %r3, 4294967295
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 4294967295)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -37,11 +40,12 @@ define zeroext i1 @f2(i32 %dummy, i32 %a, ptr %res) {
; Check that negative values are treated as unsigned
define zeroext i1 @f3(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: alfi %r3, 4294967295
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alfi %r3, 4294967295
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 -1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -52,10 +56,12 @@ define zeroext i1 @f3(i32 %dummy, i32 %a, ptr %res) {
; Check using the overflow result for a branch.
define void @f4(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: alfi %r3, 1
-; CHECK: st %r3, 0(%r4)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alfi %r3, 1
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB3_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -73,10 +79,12 @@ exit:
; ... and the same with the inverted direction.
define void @f5(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: alfi %r3, 1
-; CHECK: st %r3, 0(%r4)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alfi %r3, 1
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB4_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-05.ll b/llvm/test/CodeGen/SystemZ/int-uadd-05.ll
index 72f9fa446c2631..975cc64225a4cb 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-05.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-05.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 64-bit addition in which the second operand is constant.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,11 +8,12 @@ declare i64 @foo()
; Check addition of 1.
define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: algfi %r3, 1
-; CHECK-DAG: stg %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algfi %r3, 1
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -22,11 +24,12 @@ define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %res) {
; Check the high end of the ALGFI range.
define zeroext i1 @f2(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: algfi %r3, 4294967295
-; CHECK-DAG: stg %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algfi %r3, 4294967295
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 4294967295)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -37,12 +40,13 @@ define zeroext i1 @f2(i64 %dummy, i64 %a, ptr %res) {
; Check the next value up, which must be loaded into a register first.
define zeroext i1 @f3(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: llihl [[REG1:%r[0-9]+]], 1
-; CHECK: algr [[REG1]], %r3
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: llihl %r0, 1
+; CHECK-NEXT: algr %r0, %r3
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 4294967296)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -53,12 +57,13 @@ define zeroext i1 @f3(i64 %dummy, i64 %a, ptr %res) {
; Likewise for negative values.
define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: lghi [[REG1:%r[0-9]+]], -1
-; CHECK: algr [[REG1]], %r3
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lghi %r0, -1
+; CHECK-NEXT: algr %r0, %r3
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 -1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -69,10 +74,12 @@ define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %res) {
; Check using the overflow result for a branch.
define void @f5(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: algfi %r3, 1
-; CHECK: stg %r3, 0(%r4)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algfi %r3, 1
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB4_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -90,10 +97,12 @@ exit:
; ... and the same with the inverted direction.
define void @f6(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: algfi %r3, 1
-; CHECK: stg %r3, 0(%r4)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algfi %r3, 1
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB5_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-06.ll b/llvm/test/CodeGen/SystemZ/int-uadd-06.ll
index 4fc3c0f52aa2ce..f080ae9f5ebc69 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-06.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-06.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test the three-operand form of 32-bit addition.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
@@ -7,11 +8,12 @@ declare i32 @foo(i32, i32, i32)
; Check ALRK.
define i32 @f1(i32 %dummy, i32 %a, i32 %b, ptr %flag) {
; CHECK-LABEL: f1:
-; CHECK: alrk %r2, %r3, %r4
-; CHECK: ipm [[REG1:%r[0-5]]]
-; CHECK: risblg [[REG2:%r[0-5]]], [[REG1]], 31, 159, 35
-; CHECK: st [[REG2]], 0(%r5)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alrk %r2, %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risblg %r0, %r0, 31, 159, 35
+; CHECK-NEXT: st %r0, 0(%r5)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -23,10 +25,12 @@ define i32 @f1(i32 %dummy, i32 %a, i32 %b, ptr %flag) {
; Check using the overflow result for a branch.
define i32 @f2(i32 %dummy, i32 %a, i32 %b) {
; CHECK-LABEL: f2:
-; CHECK: alrk %r2, %r3, %r4
-; CHECK-NEXT: bler %r14
-; CHECK: lhi %r2, 0
-; CHECK: jg foo at PLT
+; CHECK: # %bb.0:
+; CHECK-NEXT: alrk %r2, %r3, %r4
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB1_1: # %call
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: jg foo at PLT
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -43,10 +47,12 @@ exit:
; ... and the same with the inverted direction.
define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
; CHECK-LABEL: f3:
-; CHECK: alrk %r2, %r3, %r4
-; CHECK-NEXT: bnler %r14
-; CHECK: lhi %r2, 0
-; CHECK: jg foo at PLT
+; CHECK: # %bb.0:
+; CHECK-NEXT: alrk %r2, %r3, %r4
+; CHECK-NEXT: bnler %r14
+; CHECK-NEXT: .LBB2_1: # %call
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: jg foo at PLT
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -63,11 +69,12 @@ exit:
; Check that we can still use ALR in obvious cases.
define i32 @f4(i32 %a, i32 %b, ptr %flag) {
; CHECK-LABEL: f4:
-; CHECK: alr %r2, %r3
-; CHECK: ipm [[REG1:%r[0-5]]]
-; CHECK: risblg [[REG2:%r[0-5]]], [[REG1]], 31, 159, 35
-; CHECK: st [[REG2]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alr %r2, %r3
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risblg %r0, %r0, 31, 159, 35
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-07.ll b/llvm/test/CodeGen/SystemZ/int-uadd-07.ll
index 873f757de8ceff..22a3353e380082 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-07.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-07.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test the three-operand form of 64-bit addition.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
@@ -7,11 +8,12 @@ declare i64 @foo(i64, i64, i64)
; Check ALGRK.
define i64 @f1(i64 %dummy, i64 %a, i64 %b, ptr %flag) {
; CHECK-LABEL: f1:
-; CHECK: algrk %r2, %r3, %r4
-; CHECK: ipm [[REG1:%r[0-5]]]
-; CHECK: risbg [[REG2:%r[0-5]]], [[REG1]], 63, 191, 35
-; CHECK: stg [[REG2]], 0(%r5)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algrk %r2, %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r0, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r0, 0(%r5)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -23,10 +25,12 @@ define i64 @f1(i64 %dummy, i64 %a, i64 %b, ptr %flag) {
; Check using the overflow result for a branch.
define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
; CHECK-LABEL: f2:
-; CHECK: algrk %r2, %r3, %r4
-; CHECK-NEXT: bler %r14
-; CHECK: lghi %r2, 0
-; CHECK: jg foo at PLT
+; CHECK: # %bb.0:
+; CHECK-NEXT: algrk %r2, %r3, %r4
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB1_1: # %call
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: jg foo at PLT
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -43,10 +47,12 @@ exit:
; ... and the same with the inverted direction.
define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
; CHECK-LABEL: f3:
-; CHECK: algrk %r2, %r3, %r4
-; CHECK-NEXT: bnler %r14
-; CHECK: lghi %r2, 0
-; CHECK: jg foo at PLT
+; CHECK: # %bb.0:
+; CHECK-NEXT: algrk %r2, %r3, %r4
+; CHECK-NEXT: bnler %r14
+; CHECK-NEXT: .LBB2_1: # %call
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: jg foo at PLT
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -63,11 +69,12 @@ exit:
; Check that we can still use ALGR in obvious cases.
define i64 @f4(i64 %a, i64 %b, ptr %flag) {
; CHECK-LABEL: f4:
-; CHECK: algr %r2, %r3
-; CHECK: ipm [[REG1:%r[0-5]]]
-; CHECK: risbg [[REG2:%r[0-5]]], [[REG1]], 63, 191, 35
-; CHECK: stg [[REG2]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algr %r2, %r3
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r0, %r0, 63, 191, 35
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-08.ll b/llvm/test/CodeGen/SystemZ/int-uadd-08.ll
index 2aab1d6c8f2a0d..9ec2db379c9eaf 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-08.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-08.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 32-bit addition in which the second operand is constant and in which
; three-operand forms are available.
;
@@ -8,11 +9,12 @@ declare i32 @foo()
; Check addition of 1.
define zeroext i1 @f1(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 1
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, 1
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -23,11 +25,12 @@ define zeroext i1 @f1(i32 %dummy, i32 %a, ptr %res) {
; Check the high end of the ALHSIK range.
define zeroext i1 @f2(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 32767
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, 32767
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 32767)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -38,11 +41,12 @@ define zeroext i1 @f2(i32 %dummy, i32 %a, ptr %res) {
; Check the next value up, which must use ALFI instead.
define zeroext i1 @f3(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: alfi %r3, 32768
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alfi %r3, 32768
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 32768)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -53,11 +57,12 @@ define zeroext i1 @f3(i32 %dummy, i32 %a, ptr %res) {
; Check the high end of the negative ALHSIK range.
define zeroext i1 @f4(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -1
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, -1
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 -1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -68,11 +73,12 @@ define zeroext i1 @f4(i32 %dummy, i32 %a, ptr %res) {
; Check the low end of the ALHSIK range.
define zeroext i1 @f5(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -32768
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, -32768
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 -32768)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -83,11 +89,12 @@ define zeroext i1 @f5(i32 %dummy, i32 %a, ptr %res) {
; Check the next value down, which must use ALFI instead.
define zeroext i1 @f6(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: alfi %r3, 4294934527
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alfi %r3, 4294934527
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 -32769)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -98,10 +105,12 @@ define zeroext i1 @f6(i32 %dummy, i32 %a, ptr %res) {
; Check using the overflow result for a branch.
define void @f7(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 1
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, 1
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB6_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -119,10 +128,12 @@ exit:
; ... and the same with the inverted direction.
define void @f8(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 1
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, 1
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB7_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-uadd-09.ll b/llvm/test/CodeGen/SystemZ/int-uadd-09.ll
index 4036f7ee655139..ad7422b6a5c5a9 100644
--- a/llvm/test/CodeGen/SystemZ/int-uadd-09.ll
+++ b/llvm/test/CodeGen/SystemZ/int-uadd-09.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 64-bit addition in which the second operand is constant and in which
; three-operand forms are available.
;
@@ -8,11 +9,12 @@ declare i64 @foo()
; Check additions of 1.
define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, 1
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, 1
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -23,11 +25,12 @@ define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %res) {
; Check the high end of the ALGHSIK range.
define zeroext i1 @f2(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, 32767
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, 32767
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 32767)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -38,11 +41,12 @@ define zeroext i1 @f2(i64 %dummy, i64 %a, ptr %res) {
; Check the next value up, which must use ALGFI instead.
define zeroext i1 @f3(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: algfi %r3, 32768
-; CHECK-DAG: stg %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: algfi %r3, 32768
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 32768)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -53,11 +57,12 @@ define zeroext i1 @f3(i64 %dummy, i64 %a, ptr %res) {
; Check the high end of the negative ALGHSIK range.
define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, -1
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, -1
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 -1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -68,11 +73,12 @@ define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %res) {
; Check the low end of the ALGHSIK range.
define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, -32768
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 35
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, -32768
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 -32768)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -83,9 +89,13 @@ define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %res) {
; Test the next value down, which cannot use either ALGHSIK or ALGFI.
define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK-NOT: alghsik
-; CHECK-NOT: algfi
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lgfi %r0, -32769
+; CHECK-NEXT: algr %r0, %r3
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 35
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 -32769)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -96,10 +106,12 @@ define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %res) {
; Check using the overflow result for a branch.
define void @f7(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, 1
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, 1
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB6_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -117,10 +129,12 @@ exit:
; ... and the same with the inverted direction.
define void @f8(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, 1
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, 1
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB7_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-01.ll b/llvm/test/CodeGen/SystemZ/int-usub-01.ll
index 6538b254fc7fdc..f9032ea64b6426 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-01.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-01.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 32-bit subtraction in which the second operand is variable.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,12 +8,13 @@ declare i32 @foo()
; Check SLR.
define zeroext i1 @f1(i32 %dummy, i32 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: slr %r3, %r4
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slr %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -23,10 +25,12 @@ define zeroext i1 @f1(i32 %dummy, i32 %a, i32 %b, ptr %res) {
; Check using the overflow result for a branch.
define void @f2(i32 %dummy, i32 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: slr %r3, %r4
-; CHECK: st %r3, 0(%r5)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slr %r3, %r4
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB1_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -44,10 +48,12 @@ exit:
; ... and the same with the inverted direction.
define void @f3(i32 %dummy, i32 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: slr %r3, %r4
-; CHECK: st %r3, 0(%r5)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slr %r3, %r4
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB2_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -65,12 +71,13 @@ exit:
; Check the low end of the SL range.
define zeroext i1 @f4(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: sl %r3, 0(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sl %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%b = load i32, ptr %src
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
@@ -82,12 +89,13 @@ define zeroext i1 @f4(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the high end of the aligned SL range.
define zeroext i1 @f5(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: sl %r3, 4092(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sl %r3, 4092(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 1023
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
@@ -100,12 +108,13 @@ define zeroext i1 @f5(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the next word up, which should use SLY instead of SL.
define zeroext i1 @f6(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: sly %r3, 4096(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sly %r3, 4096(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 1024
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
@@ -118,12 +127,13 @@ define zeroext i1 @f6(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the high end of the aligned SLY range.
define zeroext i1 @f7(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: sly %r3, 524284(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sly %r3, 524284(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 131071
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
@@ -137,13 +147,14 @@ define zeroext i1 @f7(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f8(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: agfi %r4, 524288
-; CHECK: sl %r3, 0(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, 524288
+; CHECK-NEXT: sl %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 131072
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
@@ -156,12 +167,13 @@ define zeroext i1 @f8(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the high end of the negative aligned SLY range.
define zeroext i1 @f9(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f9:
-; CHECK: sly %r3, -4(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sly %r3, -4(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -1
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
@@ -174,12 +186,13 @@ define zeroext i1 @f9(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check the low end of the SLY range.
define zeroext i1 @f10(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f10:
-; CHECK: sly %r3, -524288(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sly %r3, -524288(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -131072
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
@@ -193,13 +206,14 @@ define zeroext i1 @f10(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f11(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f11:
-; CHECK: agfi %r4, -524292
-; CHECK: sl %r3, 0(%r4)
-; CHECK-DAG: st %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, -524292
+; CHECK-NEXT: sl %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -131073
%b = load i32, ptr %ptr
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
@@ -212,12 +226,13 @@ define zeroext i1 @f11(i32 %dummy, i32 %a, ptr %src, ptr %res) {
; Check that SL allows an index.
define zeroext i1 @f12(i64 %src, i64 %index, i32 %a, ptr %res) {
; CHECK-LABEL: f12:
-; CHECK: sl %r4, 4092({{%r3,%r2|%r2,%r3}})
-; CHECK-DAG: st %r4, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sl %r4, 4092(%r3,%r2)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r4, 0(%r5)
+; CHECK-NEXT: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 4092
%ptr = inttoptr i64 %add2 to ptr
@@ -232,12 +247,13 @@ define zeroext i1 @f12(i64 %src, i64 %index, i32 %a, ptr %res) {
; Check that SLY allows an index.
define zeroext i1 @f13(i64 %src, i64 %index, i32 %a, ptr %res) {
; CHECK-LABEL: f13:
-; CHECK: sly %r4, 4096({{%r3,%r2|%r2,%r3}})
-; CHECK-DAG: st %r4, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: sly %r4, 4096(%r3,%r2)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r4, 0(%r5)
+; CHECK-NEXT: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 4096
%ptr = inttoptr i64 %add2 to ptr
@@ -252,9 +268,74 @@ define zeroext i1 @f13(i64 %src, i64 %index, i32 %a, ptr %res) {
; Check that subtractions of spilled values can use SL rather than SLR.
define zeroext i1 @f14(ptr %ptr0) {
; CHECK-LABEL: f14:
-; CHECK: brasl %r14, foo at PLT
-; CHECK: sl %r2, 16{{[04]}}(%r15)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: l %r6, 0(%r2)
+; CHECK-NEXT: l %r13, 8(%r2)
+; CHECK-NEXT: l %r12, 16(%r2)
+; CHECK-NEXT: l %r7, 24(%r2)
+; CHECK-NEXT: l %r8, 32(%r2)
+; CHECK-NEXT: l %r9, 40(%r2)
+; CHECK-NEXT: l %r10, 48(%r2)
+; CHECK-NEXT: l %r11, 56(%r2)
+; CHECK-NEXT: mvc 160(4,%r15), 64(%r2) # 4-byte Folded Spill
+; CHECK-NEXT: mvc 164(4,%r15), 72(%r2) # 4-byte Folded Spill
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: slr %r2, %r6
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: srl %r0, 31
+; CHECK-NEXT: slr %r2, %r13
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slr %r2, %r12
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slr %r2, %r7
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slr %r2, %r8
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slr %r2, %r9
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slr %r2, %r10
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slr %r2, %r11
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: sl %r2, 160(%r15) # 4-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: sl %r2, 164(%r15) # 4-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 0
+; CHECK-NEXT: lmg %r6, %r15, 216(%r15)
+; CHECK-NEXT: br %r14
%ptr1 = getelementptr i32, ptr %ptr0, i64 2
%ptr2 = getelementptr i32, ptr %ptr0, i64 4
%ptr3 = getelementptr i32, ptr %ptr0, i64 6
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-02.ll b/llvm/test/CodeGen/SystemZ/int-usub-02.ll
index 44c0e0ca5062fe..cda1a1ca8da8ec 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-02.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-02.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 64-bit subtraction in which the second operand is variable.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,12 +8,13 @@ declare i64 @foo()
; Check SLGR.
define zeroext i1 @f1(i64 %dummy, i64 %a, i64 %b, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: slgr %r3, %r4
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgr %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -23,10 +25,12 @@ define zeroext i1 @f1(i64 %dummy, i64 %a, i64 %b, ptr %res) {
; Check using the overflow result for a branch.
define void @f2(i64 %dummy, i64 %a, i64 %b, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: slgr %r3, %r4
-; CHECK: stg %r3, 0(%r5)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgr %r3, %r4
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB1_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -44,10 +48,12 @@ exit:
; ... and the same with the inverted direction.
define void @f3(i64 %dummy, i64 %a, i64 %b, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: slgr %r3, %r4
-; CHECK: stg %r3, 0(%r5)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgr %r3, %r4
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB2_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -65,12 +71,13 @@ exit:
; Check SLG with no displacement.
define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: slg %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slg %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%b = load i64, ptr %src
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
@@ -82,12 +89,13 @@ define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the high end of the aligned SLG range.
define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: slg %r3, 524280(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slg %r3, 524280(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 65535
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
@@ -101,13 +109,14 @@ define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: agfi %r4, 524288
-; CHECK: slg %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, 524288
+; CHECK-NEXT: slg %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 65536
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
@@ -120,12 +129,13 @@ define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the high end of the negative aligned SLG range.
define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: slg %r3, -8(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slg %r3, -8(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 -1
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
@@ -138,12 +148,13 @@ define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the low end of the SLG range.
define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: slg %r3, -524288(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slg %r3, -524288(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 -65536
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
@@ -157,13 +168,14 @@ define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f9:
-; CHECK: agfi %r4, -524296
-; CHECK: slg %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, -524296
+; CHECK-NEXT: slg %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i64, ptr %src, i64 -65537
%b = load i64, ptr %ptr
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
@@ -176,12 +188,13 @@ define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check that SLG allows an index.
define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {
; CHECK-LABEL: f10:
-; CHECK: slg %r4, 524280({{%r3,%r2|%r2,%r3}})
-; CHECK-DAG: stg %r4, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slg %r4, 524280(%r3,%r2)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r4, 0(%r5)
+; CHECK-NEXT: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524280
%ptr = inttoptr i64 %add2 to ptr
@@ -196,9 +209,74 @@ define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {
; Check that subtractions of spilled values can use SLG rather than SLGR.
define zeroext i1 @f11(ptr %ptr0) {
; CHECK-LABEL: f11:
-; CHECK: brasl %r14, foo at PLT
-; CHECK: slg %r2, 160(%r15)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -176
+; CHECK-NEXT: .cfi_def_cfa_offset 336
+; CHECK-NEXT: lg %r6, 0(%r2)
+; CHECK-NEXT: lg %r13, 16(%r2)
+; CHECK-NEXT: lg %r12, 32(%r2)
+; CHECK-NEXT: lg %r7, 48(%r2)
+; CHECK-NEXT: lg %r8, 64(%r2)
+; CHECK-NEXT: lg %r9, 80(%r2)
+; CHECK-NEXT: lg %r10, 96(%r2)
+; CHECK-NEXT: lg %r11, 112(%r2)
+; CHECK-NEXT: mvc 160(8,%r15), 128(%r2) # 8-byte Folded Spill
+; CHECK-NEXT: mvc 168(8,%r15), 144(%r2) # 8-byte Folded Spill
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: slgr %r2, %r6
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: srl %r0, 31
+; CHECK-NEXT: slgr %r2, %r13
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgr %r2, %r12
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgr %r2, %r7
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgr %r2, %r8
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgr %r2, %r9
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgr %r2, %r10
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgr %r2, %r11
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slg %r2, 160(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slg %r2, 168(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 0
+; CHECK-NEXT: lmg %r6, %r15, 224(%r15)
+; CHECK-NEXT: br %r14
%ptr1 = getelementptr i64, ptr %ptr0, i64 2
%ptr2 = getelementptr i64, ptr %ptr0, i64 4
%ptr3 = getelementptr i64, ptr %ptr0, i64 6
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-03.ll b/llvm/test/CodeGen/SystemZ/int-usub-03.ll
index 30672cbc72f9fe..83c3db41992553 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-03.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-03.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test subtraction of a zero-extended i32 from an i64.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,12 +8,13 @@ declare i64 @foo()
; Check SLGFR.
define zeroext i1 @f1(i64 %dummy, i64 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: slgfr %r3, %r4
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgfr %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%bext = zext i32 %b to i64
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %bext)
%val = extractvalue {i64, i1} %t, 0
@@ -24,10 +26,12 @@ define zeroext i1 @f1(i64 %dummy, i64 %a, i32 %b, ptr %res) {
; Check using the overflow result for a branch.
define void @f2(i64 %dummy, i64 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: slgfr %r3, %r4
-; CHECK: stg %r3, 0(%r5)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgfr %r3, %r4
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB1_1: # %exit
+; CHECK-NEXT: br %r14
%bext = zext i32 %b to i64
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %bext)
%val = extractvalue {i64, i1} %t, 0
@@ -46,10 +50,12 @@ exit:
; ... and the same with the inverted direction.
define void @f3(i64 %dummy, i64 %a, i32 %b, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: slgfr %r3, %r4
-; CHECK: stg %r3, 0(%r5)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgfr %r3, %r4
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB2_1: # %exit
+; CHECK-NEXT: br %r14
%bext = zext i32 %b to i64
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %bext)
%val = extractvalue {i64, i1} %t, 0
@@ -68,12 +74,13 @@ exit:
; Check SLGF with no displacement.
define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: slgf %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgf %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%b = load i32, ptr %src
%bext = zext i32 %b to i64
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %bext)
@@ -86,12 +93,13 @@ define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the high end of the aligned SLGF range.
define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: slgf %r3, 524284(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgf %r3, 524284(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 131071
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -106,13 +114,14 @@ define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: agfi %r4, 524288
-; CHECK: slgf %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, 524288
+; CHECK-NEXT: slgf %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 131072
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -126,12 +135,13 @@ define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the high end of the negative aligned SLGF range.
define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: slgf %r3, -4(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgf %r3, -4(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -1
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -145,12 +155,13 @@ define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check the low end of the SLGF range.
define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: slgf %r3, -524288(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgf %r3, -524288(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -131072
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -165,13 +176,14 @@ define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Other sequences besides this one would be OK.
define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; CHECK-LABEL: f9:
-; CHECK: agfi %r4, -524292
-; CHECK: slgf %r3, 0(%r4)
-; CHECK-DAG: stg %r3, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: agfi %r4, -524292
+; CHECK-NEXT: slgf %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r5)
+; CHECK-NEXT: br %r14
%ptr = getelementptr i32, ptr %src, i64 -131073
%b = load i32, ptr %ptr
%bext = zext i32 %b to i64
@@ -185,12 +197,13 @@ define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {
; Check that SLGF allows an index.
define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {
; CHECK-LABEL: f10:
-; CHECK: slgf %r4, 524284({{%r3,%r2|%r2,%r3}})
-; CHECK-DAG: stg %r4, 0(%r5)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgf %r4, 524284(%r3,%r2)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r4, 0(%r5)
+; CHECK-NEXT: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524284
%ptr = inttoptr i64 %add2 to ptr
@@ -206,9 +219,96 @@ define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {
; Check that subtractions of spilled values can use SLGF rather than SLGFR.
define zeroext i1 @f11(ptr %ptr0) {
; CHECK-LABEL: f11:
-; CHECK: brasl %r14, foo at PLT
-; CHECK: slgf {{%r[0-9]+}}, 160(%r15)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -168
+; CHECK-NEXT: .cfi_def_cfa_offset 328
+; CHECK-NEXT: lhi %r0, 100
+; CHECK-NEXT: lhi %r12, 100
+; CHECK-NEXT: a %r12, 0(%r2)
+; CHECK-NEXT: lhi %r13, 100
+; CHECK-NEXT: a %r13, 8(%r2)
+; CHECK-NEXT: lhi %r6, 100
+; CHECK-NEXT: a %r6, 16(%r2)
+; CHECK-NEXT: lhi %r7, 100
+; CHECK-NEXT: a %r7, 24(%r2)
+; CHECK-NEXT: lhi %r8, 100
+; CHECK-NEXT: a %r8, 32(%r2)
+; CHECK-NEXT: lhi %r9, 100
+; CHECK-NEXT: a %r9, 40(%r2)
+; CHECK-NEXT: lhi %r10, 100
+; CHECK-NEXT: a %r10, 48(%r2)
+; CHECK-NEXT: lhi %r11, 100
+; CHECK-NEXT: a %r11, 56(%r2)
+; CHECK-NEXT: lhi %r1, 100
+; CHECK-NEXT: a %r1, 64(%r2)
+; CHECK-NEXT: st %r1, 160(%r15) # 4-byte Folded Spill
+; CHECK-NEXT: a %r0, 72(%r2)
+; CHECK-NEXT: st %r0, 164(%r15) # 4-byte Folded Spill
+; CHECK-NEXT: st %r12, 0(%r2)
+; CHECK-NEXT: st %r13, 8(%r2)
+; CHECK-NEXT: st %r6, 16(%r2)
+; CHECK-NEXT: st %r7, 24(%r2)
+; CHECK-NEXT: st %r8, 32(%r2)
+; CHECK-NEXT: st %r9, 40(%r2)
+; CHECK-NEXT: st %r10, 48(%r2)
+; CHECK-NEXT: st %r11, 56(%r2)
+; CHECK-NEXT: st %r1, 64(%r2)
+; CHECK-NEXT: st %r0, 72(%r2)
+; CHECK-NEXT: brasl %r14, foo at PLT
+; CHECK-NEXT: slgfr %r2, %r12
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: srl %r0, 31
+; CHECK-NEXT: slgfr %r2, %r13
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgfr %r2, %r6
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgfr %r2, %r7
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgfr %r2, %r8
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgfr %r2, %r9
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgfr %r2, %r10
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgfr %r2, %r11
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgf %r2, 160(%r15) # 4-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: slgf %r2, 164(%r15) # 4-byte Folded Reload
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: rosbg %r0, %r1, 63, 63, 33
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 0
+; CHECK-NEXT: lmg %r6, %r15, 216(%r15)
+; CHECK-NEXT: br %r14
%ptr1 = getelementptr i32, ptr %ptr0, i64 2
%ptr2 = getelementptr i32, ptr %ptr0, i64 4
%ptr3 = getelementptr i32, ptr %ptr0, i64 6
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-04.ll b/llvm/test/CodeGen/SystemZ/int-usub-04.ll
index 79728ec2302e5f..bab360e94b80e1 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-04.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-04.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 32-bit subtraction in which the second operand is constant.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,12 +8,13 @@ declare i32 @foo()
; Check subtraction of 1.
define zeroext i1 @f1(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: slfi %r3, 1
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slfi %r3, 1
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -23,12 +25,13 @@ define zeroext i1 @f1(i32 %dummy, i32 %a, ptr %res) {
; Check the high end of the SLFI range.
define zeroext i1 @f2(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: slfi %r3, 4294967295
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slfi %r3, 4294967295
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 4294967295)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -39,12 +42,13 @@ define zeroext i1 @f2(i32 %dummy, i32 %a, ptr %res) {
; Check that negative values are treated as unsigned
define zeroext i1 @f3(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: slfi %r3, 4294967295
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slfi %r3, 4294967295
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 -1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -55,10 +59,12 @@ define zeroext i1 @f3(i32 %dummy, i32 %a, ptr %res) {
; Check using the overflow result for a branch.
define void @f4(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: slfi %r3, 1
-; CHECK: st %r3, 0(%r4)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slfi %r3, 1
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB3_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -76,10 +82,12 @@ exit:
; ... and the same with the inverted direction.
define void @f5(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: slfi %r3, 1
-; CHECK: st %r3, 0(%r4)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slfi %r3, 1
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB4_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-05.ll b/llvm/test/CodeGen/SystemZ/int-usub-05.ll
index 8bb5ae6af3d3ee..7e275b2c0e0dcf 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-05.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-05.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 64-bit subtraction in which the second operand is constant.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
@@ -7,12 +8,13 @@ declare i64 @foo()
; Check addition of 1.
define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: slgfi %r3, 1
-; CHECK-DAG: stg %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgfi %r3, 1
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -23,12 +25,13 @@ define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %res) {
; Check the high end of the SLGFI range.
define zeroext i1 @f2(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: slgfi %r3, 4294967295
-; CHECK-DAG: stg %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgfi %r3, 4294967295
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 4294967295)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -39,13 +42,14 @@ define zeroext i1 @f2(i64 %dummy, i64 %a, ptr %res) {
; Check the next value up, which must be loaded into a register first.
define zeroext i1 @f3(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: llihl [[REG1:%r[0-9]+]], 1
-; CHECK: slgr %r3, [[REG1]]
-; CHECK-DAG: stg %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: llihl %r0, 1
+; CHECK-NEXT: slgr %r3, %r0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 4294967296)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -56,13 +60,14 @@ define zeroext i1 @f3(i64 %dummy, i64 %a, ptr %res) {
; Likewise for negative values.
define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: lghi [[REG1:%r[0-9]+]], -1
-; CHECK: slgr %r3, [[REG1]]
-; CHECK-DAG: stg %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lghi %r0, -1
+; CHECK-NEXT: slgr %r3, %r0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 -1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -73,10 +78,12 @@ define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %res) {
; Check using the overflow result for a branch.
define void @f5(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: slgfi %r3, 1
-; CHECK: stg %r3, 0(%r4)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgfi %r3, 1
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB4_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -94,10 +101,12 @@ exit:
; ... and the same with the inverted direction.
define void @f6(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: slgfi %r3, 1
-; CHECK: stg %r3, 0(%r4)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgfi %r3, 1
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB5_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-06.ll b/llvm/test/CodeGen/SystemZ/int-usub-06.ll
index dfcac63ed5485c..f3e69b92933305 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-06.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-06.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test the three-operand form of 32-bit subtraction.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
@@ -7,12 +8,13 @@ declare i32 @foo(i32, i32, i32)
; Check SLRK.
define i32 @f1(i32 %dummy, i32 %a, i32 %b, ptr %flag) {
; CHECK-LABEL: f1:
-; CHECK: slrk %r2, %r3, %r4
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: afi [[REG]], -536870912
-; CHECK: srl [[REG]], 31
-; CHECK: st [[REG]], 0(%r5)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slrk %r2, %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: srl %r0, 31
+; CHECK-NEXT: st %r0, 0(%r5)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -24,10 +26,12 @@ define i32 @f1(i32 %dummy, i32 %a, i32 %b, ptr %flag) {
; Check using the overflow result for a branch.
define i32 @f2(i32 %dummy, i32 %a, i32 %b) {
; CHECK-LABEL: f2:
-; CHECK: slrk %r2, %r3, %r4
-; CHECK-NEXT: bnler %r14
-; CHECK: lhi %r2, 0
-; CHECK: jg foo at PLT
+; CHECK: # %bb.0:
+; CHECK-NEXT: slrk %r2, %r3, %r4
+; CHECK-NEXT: bnler %r14
+; CHECK-NEXT: .LBB1_1: # %call
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: jg foo at PLT
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -44,10 +48,12 @@ exit:
; ... and the same with the inverted direction.
define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
; CHECK-LABEL: f3:
-; CHECK: slrk %r2, %r3, %r4
-; CHECK-NEXT: bler %r14
-; CHECK: lhi %r2, 0
-; CHECK: jg foo at PLT
+; CHECK: # %bb.0:
+; CHECK-NEXT: slrk %r2, %r3, %r4
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB2_1: # %call
+; CHECK-NEXT: lhi %r2, 0
+; CHECK-NEXT: jg foo at PLT
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -64,12 +70,13 @@ exit:
; Check that we can still use SLR in obvious cases.
define i32 @f4(i32 %a, i32 %b, ptr %flag) {
; CHECK-LABEL: f4:
-; CHECK: slr %r2, %r3
-; CHECK: ipm [[REG:%r[0-5]]]
-; CHECK: afi [[REG]], -536870912
-; CHECK: srl [[REG]], 31
-; CHECK: st [[REG]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slr %r2, %r3
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: srl %r0, 31
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-07.ll b/llvm/test/CodeGen/SystemZ/int-usub-07.ll
index 4136b476c7e628..ce8147242bd5cc 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-07.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-07.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test the three-operand form of 64-bit addition.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
@@ -7,12 +8,13 @@ declare i64 @foo(i64, i64, i64)
; Check SLGRK.
define i64 @f1(i64 %dummy, i64 %a, i64 %b, ptr %flag) {
; CHECK-LABEL: f1:
-; CHECK: slgrk %r2, %r3, %r4
-; CHECK: ipm [[REG1:%r[0-5]]]
-; CHECK: afi [[REG1]], -536870912
-; CHECK: risbg [[REG2:%r[0-5]]], [[REG1]], 63, 191, 33
-; CHECK: stg [[REG2]], 0(%r5)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgrk %r2, %r3, %r4
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r0, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r0, 0(%r5)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -24,10 +26,12 @@ define i64 @f1(i64 %dummy, i64 %a, i64 %b, ptr %flag) {
; Check using the overflow result for a branch.
define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
; CHECK-LABEL: f2:
-; CHECK: slgrk %r2, %r3, %r4
-; CHECK-NEXT: bnler %r14
-; CHECK: lghi %r2, 0
-; CHECK: jg foo at PLT
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgrk %r2, %r3, %r4
+; CHECK-NEXT: bnler %r14
+; CHECK-NEXT: .LBB1_1: # %call
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: jg foo at PLT
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -44,10 +48,12 @@ exit:
; ... and the same with the inverted direction.
define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
; CHECK-LABEL: f3:
-; CHECK: slgrk %r2, %r3, %r4
-; CHECK-NEXT: bler %r14
-; CHECK: lghi %r2, 0
-; CHECK: jg foo at PLT
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgrk %r2, %r3, %r4
+; CHECK-NEXT: bler %r14
+; CHECK-NEXT: .LBB2_1: # %call
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: jg foo at PLT
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -64,12 +70,13 @@ exit:
; Check that we can still use SLGR in obvious cases.
define i64 @f4(i64 %a, i64 %b, ptr %flag) {
; CHECK-LABEL: f4:
-; CHECK: slgr %r2, %r3
-; CHECK: ipm [[REG1:%r[0-5]]]
-; CHECK: afi [[REG1]], -536870912
-; CHECK: risbg [[REG2:%r[0-5]]], [[REG1]], 63, 191, 33
-; CHECK: stg [[REG2]], 0(%r4)
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgr %r2, %r3
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r0, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-08.ll b/llvm/test/CodeGen/SystemZ/int-usub-08.ll
index d02caabf9fbe3f..ff674406266b7e 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-08.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-08.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 32-bit subtraction in which the second operand is constant and in which
; three-operand forms are available.
;
@@ -8,12 +9,13 @@ declare i32 @foo()
; Check subtraction of 1.
define zeroext i1 @f1(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -1
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, -1
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -24,12 +26,13 @@ define zeroext i1 @f1(i32 %dummy, i32 %a, ptr %res) {
; Check the high end of the ALHSIK range.
define zeroext i1 @f2(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -32768
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, -32768
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 32768)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -40,12 +43,13 @@ define zeroext i1 @f2(i32 %dummy, i32 %a, ptr %res) {
; Check the next value down, which must use SLFI instead.
define zeroext i1 @f3(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: slfi %r3, 32769
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slfi %r3, 32769
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 32769)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -56,12 +60,13 @@ define zeroext i1 @f3(i32 %dummy, i32 %a, ptr %res) {
; Check the high end of the negative ALHSIK range.
define zeroext i1 @f4(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 1
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, 1
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 -1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -72,12 +77,13 @@ define zeroext i1 @f4(i32 %dummy, i32 %a, ptr %res) {
; Check the low end of the ALHSIK range.
define zeroext i1 @f5(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, 32767
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, 32767
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 -32767)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -88,12 +94,13 @@ define zeroext i1 @f5(i32 %dummy, i32 %a, ptr %res) {
; Check the next value down, which must use SLFI instead.
define zeroext i1 @f6(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK: slfi %r3, 4294934528
-; CHECK-DAG: st %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slfi %r3, 4294934528
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 -32768)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -104,10 +111,12 @@ define zeroext i1 @f6(i32 %dummy, i32 %a, ptr %res) {
; Check using the overflow result for a branch.
define void @f7(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -1
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, -1
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB6_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@@ -125,10 +134,12 @@ exit:
; ... and the same with the inverted direction.
define void @f8(i32 %dummy, i32 %a, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: alhsik [[REG1:%r[0-5]]], %r3, -1
-; CHECK-DAG: st [[REG1]], 0(%r4)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alhsik %r0, %r3, -1
+; CHECK-NEXT: st %r0, 0(%r4)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB7_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 1)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
diff --git a/llvm/test/CodeGen/SystemZ/int-usub-09.ll b/llvm/test/CodeGen/SystemZ/int-usub-09.ll
index 741e59caf78fb2..4bdc65cb9007ef 100644
--- a/llvm/test/CodeGen/SystemZ/int-usub-09.ll
+++ b/llvm/test/CodeGen/SystemZ/int-usub-09.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test 64-bit addition in which the second operand is constant and in which
; three-operand forms are available.
;
@@ -8,12 +9,13 @@ declare i64 @foo()
; Check subtraction of 1.
define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f1:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, -1
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, -1
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -24,12 +26,13 @@ define zeroext i1 @f1(i64 %dummy, i64 %a, ptr %res) {
; Check the high end of the ALGHSIK range.
define zeroext i1 @f2(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f2:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, -32768
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, -32768
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 32768)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -40,12 +43,13 @@ define zeroext i1 @f2(i64 %dummy, i64 %a, ptr %res) {
; Check the next value up, which must use SLGFI instead.
define zeroext i1 @f3(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f3:
-; CHECK: slgfi %r3, 32769
-; CHECK-DAG: stg %r3, 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: slgfi %r3, 32769
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 32769)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -56,12 +60,13 @@ define zeroext i1 @f3(i64 %dummy, i64 %a, ptr %res) {
; Check the high end of the negative ALGHSIK range.
define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f4:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, 1
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, 1
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 -1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -72,12 +77,13 @@ define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %res) {
; Check the low end of the ALGHSIK range.
define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f5:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, 32767
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK-DAG: ipm [[REG2:%r[0-5]]]
-; CHECK-DAG: afi [[REG2]], -536870912
-; CHECK-DAG: risbg %r2, [[REG2]], 63, 191, 33
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, 32767
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: ipm %r1
+; CHECK-NEXT: afi %r1, -536870912
+; CHECK-NEXT: risbg %r2, %r1, 63, 191, 33
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 -32767)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -88,9 +94,14 @@ define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %res) {
; Test the next value down, which cannot use either ALGHSIK or SLGFI.
define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f6:
-; CHECK-NOT: alghsik
-; CHECK-NOT: slgfi
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: lghi %r0, -32768
+; CHECK-NEXT: slgr %r3, %r0
+; CHECK-NEXT: ipm %r0
+; CHECK-NEXT: afi %r0, -536870912
+; CHECK-NEXT: risbg %r2, %r0, 63, 191, 33
+; CHECK-NEXT: stg %r3, 0(%r4)
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 -32768)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -101,10 +112,12 @@ define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %res) {
; Check using the overflow result for a branch.
define void @f7(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f7:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, -1
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK: jgle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, -1
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: jgle foo at PLT
+; CHECK-NEXT: .LBB6_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@@ -122,10 +135,12 @@ exit:
; ... and the same with the inverted direction.
define void @f8(i64 %dummy, i64 %a, ptr %res) {
; CHECK-LABEL: f8:
-; CHECK: alghsik [[REG1:%r[0-5]]], %r3, -1
-; CHECK-DAG: stg [[REG1]], 0(%r4)
-; CHECK: jgnle foo at PLT
-; CHECK: br %r14
+; CHECK: # %bb.0:
+; CHECK-NEXT: alghsik %r0, %r3, -1
+; CHECK-NEXT: stg %r0, 0(%r4)
+; CHECK-NEXT: jgnle foo at PLT
+; CHECK-NEXT: .LBB7_1: # %exit
+; CHECK-NEXT: br %r14
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 1)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
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