[PATCH] D154141: [RISCV] Remove legacy TA/TU pseudo distinction for load instructions

[Philip Reames via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG403261eafd0f: [RISCV] Remove legacy TA/TU pseudo distinction for load instructions (authored by reames).

Changed prior to commit:
  https://reviews.llvm.org/D154141?vs=535960&id=537473#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154141/new/

https://reviews.llvm.org/D154141

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir
  llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
  llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
  llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
  llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/stepvector.ll
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
  llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
  llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
  llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

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