[llvm] 1039aec - [RISCV] Fix interleave/deinterleave store test output

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2023-07-05T19:52:50+01:00
New Revision: 1039aec30b4a27979c8c1163818ecdd9c5723aab

URL: https://github.com/llvm/llvm-project/commit/1039aec30b4a27979c8c1163818ecdd9c5723aab
DIFF: https://github.com/llvm/llvm-project/commit/1039aec30b4a27979c8c1163818ecdd9c5723aab.diff

LOG: [RISCV] Fix interleave/deinterleave store test output

Looks like the output changed after rebasing

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
    llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
index f6aaece61fd1e7..e13604ee6b7f34 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
@@ -20,12 +20,12 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
 ; RV32-NEXT:    vid.v v9
 ; RV32-NEXT:    vadd.vv v11, v9, v9
 ; RV32-NEXT:    vrgather.vv v9, v8, v11
-; RV32-NEXT:    vadd.vi v12, v11, -16
 ; RV32-NEXT:    lui a0, 16
 ; RV32-NEXT:    addi a0, a0, -256
 ; RV32-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
 ; RV32-NEXT:    vmv.v.x v0, a0
 ; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; RV32-NEXT:    vadd.vi v12, v11, -16
 ; RV32-NEXT:    vrgather.vv v9, v10, v12, v0.t
 ; RV32-NEXT:    vmsne.vi v9, v9, 0
 ; RV32-NEXT:    vadd.vi v12, v11, 1
@@ -51,12 +51,12 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
 ; RV64-NEXT:    vid.v v9
 ; RV64-NEXT:    vadd.vv v11, v9, v9
 ; RV64-NEXT:    vrgather.vv v9, v8, v11
-; RV64-NEXT:    vadd.vi v12, v11, -16
 ; RV64-NEXT:    lui a0, 16
 ; RV64-NEXT:    addiw a0, a0, -256
 ; RV64-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
 ; RV64-NEXT:    vmv.v.x v0, a0
 ; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; RV64-NEXT:    vadd.vi v12, v11, -16
 ; RV64-NEXT:    vrgather.vv v9, v10, v12, v0.t
 ; RV64-NEXT:    vmsne.vi v9, v9, 0
 ; RV64-NEXT:    vadd.vi v12, v11, 1

diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll
index 431f8be2accc8c..e2ff4ecd18403f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll
@@ -7,12 +7,13 @@
 define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr %p) {
 ; CHECK-LABEL: vector_interleave_store_v32i1_v16i1:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a1, 32
+; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT:    vmv.v.i v10, 0
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; CHECK-NEXT:    vslideup.vi v0, v8, 2
-; CHECK-NEXT:    li a1, 32
 ; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 0
-; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vmerge.vim v8, v10, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m2, ta, ma
 ; CHECK-NEXT:    vslidedown.vi v10, v8, 16
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma