[llvm] ea62fc7 - [RISCV] Lower deinterleave2 intrinsics to vlseg2
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 5 11:24:26 PDT 2023
Author: Luke Lau
Date: 2023-07-05T19:24:15+01:00
New Revision: ea62fc79e7f95a73288e6d2402d30f91681849b6
URL: https://github.com/llvm/llvm-project/commit/ea62fc79e7f95a73288e6d2402d30f91681849b6
DIFF: https://github.com/llvm/llvm-project/commit/ea62fc79e7f95a73288e6d2402d30f91681849b6.diff
LOG: [RISCV] Lower deinterleave2 intrinsics to vlseg2
Following from D153864, this patch implements the lowerDeinterleaveIntrinsic
hook to lower deinterleaves of loads into vlseg2 intrinsics.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D153876
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index cf079cc62d5dbd..25d376c9ecfbeb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16720,6 +16720,12 @@ bool RISCVTargetLowering::isLegalStridedLoadStore(EVT DataType,
return true;
}
+static const Intrinsic::ID FixedVlsegIntrIds[] = {
+ Intrinsic::riscv_seg2_load, Intrinsic::riscv_seg3_load,
+ Intrinsic::riscv_seg4_load, Intrinsic::riscv_seg5_load,
+ Intrinsic::riscv_seg6_load, Intrinsic::riscv_seg7_load,
+ Intrinsic::riscv_seg8_load};
+
/// Lower an interleaved load into a vlsegN intrinsic.
///
/// E.g. Lower an interleaved load (Factor = 2):
@@ -16744,13 +16750,8 @@ bool RISCVTargetLowering::lowerInterleavedLoad(
auto *XLenTy = Type::getIntNTy(LI->getContext(), Subtarget.getXLen());
- static const Intrinsic::ID FixedLenIntrIds[] = {
- Intrinsic::riscv_seg2_load, Intrinsic::riscv_seg3_load,
- Intrinsic::riscv_seg4_load, Intrinsic::riscv_seg5_load,
- Intrinsic::riscv_seg6_load, Intrinsic::riscv_seg7_load,
- Intrinsic::riscv_seg8_load};
Function *VlsegNFunc =
- Intrinsic::getDeclaration(LI->getModule(), FixedLenIntrIds[Factor - 2],
+ Intrinsic::getDeclaration(LI->getModule(), FixedVlsegIntrIds[Factor - 2],
{VTy, LI->getPointerOperandType(), XLenTy});
Value *VL = ConstantInt::get(XLenTy, VTy->getNumElements());
@@ -16826,6 +16827,55 @@ bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI,
return true;
}
+bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI,
+ LoadInst *LI) const {
+ assert(LI->isSimple());
+ IRBuilder<> Builder(LI);
+
+ // Only deinterleave2 supported at present.
+ if (DI->getIntrinsicID() != Intrinsic::experimental_vector_deinterleave2)
+ return false;
+
+ unsigned Factor = 2;
+
+ VectorType *VTy = cast<VectorType>(DI->getOperand(0)->getType());
+ VectorType *ResVTy = cast<VectorType>(DI->getType()->getContainedType(0));
+
+ if (!isLegalInterleavedAccessType(ResVTy, Factor,
+ LI->getModule()->getDataLayout()))
+ return false;
+
+ Function *VlsegNFunc;
+ Value *VL;
+ Type *XLenTy = Type::getIntNTy(LI->getContext(), Subtarget.getXLen());
+ SmallVector<Value *, 10> Ops;
+
+ if (auto *FVTy = dyn_cast<FixedVectorType>(VTy)) {
+ VlsegNFunc = Intrinsic::getDeclaration(
+ LI->getModule(), FixedVlsegIntrIds[Factor - 2],
+ {ResVTy, LI->getPointerOperandType(), XLenTy});
+ VL = ConstantInt::get(XLenTy, FVTy->getNumElements());
+ } else {
+ static const Intrinsic::ID IntrIds[] = {
+ Intrinsic::riscv_vlseg2, Intrinsic::riscv_vlseg3,
+ Intrinsic::riscv_vlseg4, Intrinsic::riscv_vlseg5,
+ Intrinsic::riscv_vlseg6, Intrinsic::riscv_vlseg7,
+ Intrinsic::riscv_vlseg8};
+
+ VlsegNFunc = Intrinsic::getDeclaration(LI->getModule(), IntrIds[Factor - 2],
+ {ResVTy, XLenTy});
+ VL = Constant::getAllOnesValue(XLenTy);
+ Ops.append(Factor, PoisonValue::get(ResVTy));
+ }
+
+ Ops.append({LI->getPointerOperand(), VL});
+
+ Value *Vlseg = Builder.CreateCall(VlsegNFunc, Ops);
+ DI->replaceAllUsesWith(Vlseg);
+
+ return true;
+}
+
bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
StoreInst *SI) const {
assert(SI->isSimple());
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index f1c9b3781ff208..87d6c9f3957217 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -759,6 +759,9 @@ class RISCVTargetLowering : public TargetLowering {
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
unsigned Factor) const override;
+ bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *II,
+ LoadInst *LI) const override;
+
bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
StoreInst *SI) const override;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
index 654ef6671f2acb..f6aaece61fd1e7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
@@ -74,12 +74,8 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
define {<16 x i8>, <16 x i8>} @vector_deinterleave_load_v16i8_v32i8(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v16i8_v32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 32
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v10, 0
-; CHECK-NEXT: vnsrl.wi v9, v10, 8
+; CHECK-NEXT: vlseg2e8.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <32 x i8>, ptr %p
%retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %vec)
@@ -89,11 +85,8 @@ define {<16 x i8>, <16 x i8>} @vector_deinterleave_load_v16i8_v32i8(ptr %p) {
define {<8 x i16>, <8 x i16>} @vector_deinterleave_load_v8i16_v16i16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v8i16_v16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v10, 0
-; CHECK-NEXT: vnsrl.wi v9, v10, 16
+; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <16 x i16>, ptr %p
%retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec)
@@ -103,12 +96,8 @@ define {<8 x i16>, <8 x i16>} @vector_deinterleave_load_v8i16_v16i16(ptr %p) {
define {<4 x i32>, <4 x i32>} @vector_deinterleave_load_v4i32_vv8i32(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v4i32_vv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vnsrl.wx v9, v10, a0
-; CHECK-NEXT: vnsrl.wi v8, v10, 0
+; CHECK-NEXT: vlseg2e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <8 x i32>, ptr %p
%retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec)
@@ -118,16 +107,8 @@ define {<4 x i32>, <4 x i32>} @vector_deinterleave_load_v4i32_vv8i32(ptr %p) {
define {<2 x i64>, <2 x i64>} @vector_deinterleave_load_v2i64_v4i64(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v2i64_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 2
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v0, 2
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v9, v8, 1
-; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v10, 1
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vlseg2e64.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <4 x i64>, ptr %p
%retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec)
@@ -145,11 +126,8 @@ declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4
define {<2 x half>, <2 x half>} @vector_deinterleave_load_v2f16_v4f16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v2f16_v4f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v9, 0
-; CHECK-NEXT: vnsrl.wi v9, v9, 16
+; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <4 x half>, ptr %p
%retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %vec)
@@ -159,11 +137,8 @@ define {<2 x half>, <2 x half>} @vector_deinterleave_load_v2f16_v4f16(ptr %p) {
define {<4 x half>, <4 x half>} @vector_deinterleave_load_v4f16_v8f16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v4f16_v8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v9, 0
-; CHECK-NEXT: vnsrl.wi v9, v9, 16
+; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <8 x half>, ptr %p
%retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %vec)
@@ -173,12 +148,8 @@ define {<4 x half>, <4 x half>} @vector_deinterleave_load_v4f16_v8f16(ptr %p) {
define {<2 x float>, <2 x float>} @vector_deinterleave_load_v2f32_v4f32(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v2f32_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wx v9, v8, a0
-; CHECK-NEXT: vnsrl.wi v8, v8, 0
+; CHECK-NEXT: vlseg2e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <4 x float>, ptr %p
%retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float> %vec)
@@ -188,11 +159,8 @@ define {<2 x float>, <2 x float>} @vector_deinterleave_load_v2f32_v4f32(ptr %p)
define {<8 x half>, <8 x half>} @vector_deinterleave_load_v8f16_v16f16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v8f16_v16f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v10, 0
-; CHECK-NEXT: vnsrl.wi v9, v10, 16
+; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <16 x half>, ptr %p
%retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %vec)
@@ -202,12 +170,8 @@ define {<8 x half>, <8 x half>} @vector_deinterleave_load_v8f16_v16f16(ptr %p) {
define {<4 x float>, <4 x float>} @vector_deinterleave_load_v4f32_v8f32(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v4f32_v8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vnsrl.wx v9, v10, a0
-; CHECK-NEXT: vnsrl.wi v8, v10, 0
+; CHECK-NEXT: vlseg2e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <8 x float>, ptr %p
%retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec)
@@ -217,16 +181,8 @@ define {<4 x float>, <4 x float>} @vector_deinterleave_load_v4f32_v8f32(ptr %p)
define {<2 x double>, <2 x double>} @vector_deinterleave_load_v2f64_v4f64(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v2f64_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
-; CHECK-NEXT: vslidedown.vi v10, v8, 2
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v0, 2
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; CHECK-NEXT: vrgather.vi v9, v8, 1
-; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t
-; CHECK-NEXT: vslideup.vi v8, v10, 1
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vlseg2e64.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <4 x double>, ptr %p
%retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
index 17bb68a6253844..5536a6ebc1510d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
@@ -31,10 +31,8 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_load_nxv16i
define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_load_nxv16i8_nxv32i8(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv16i8_nxv32i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4r.v v12, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vnsrl.wi v10, v12, 8
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vlseg2e8.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 32 x i8>, ptr %p
%retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
@@ -44,10 +42,8 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_load_nxv16i
define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_load_nxv8i16_nxv16i16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv8i16_nxv16i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re16.v v12, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vnsrl.wi v10, v12, 16
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 16 x i16>, ptr %p
%retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
@@ -57,11 +53,8 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_load_nxv8i1
define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_load_nxv4i32_nxvv8i32(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv4i32_nxvv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re32.v v12, (a0)
-; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vnsrl.wx v10, v12, a0
-; CHECK-NEXT: vnsrl.wi v8, v12, 0
+; CHECK-NEXT: vlseg2e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 8 x i32>, ptr %p
%retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)
@@ -71,14 +64,8 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_load_nxv4i3
define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_load_nxv2i64_nxv4i64(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv2i64_nxv4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re64.v v12, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vadd.vv v16, v8, v8
-; CHECK-NEXT: vrgather.vv v8, v12, v16
-; CHECK-NEXT: vadd.vi v16, v16, 1
-; CHECK-NEXT: vrgather.vv v20, v12, v16
-; CHECK-NEXT: vmv2r.v v10, v20
+; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT: vlseg2e64.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 4 x i64>, ptr %p
%retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)
@@ -88,14 +75,8 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_load_nxv2i6
define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_load_nxv4i64_nxv8i64(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv4i64_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re64.v v16, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vadd.vv v24, v8, v8
-; CHECK-NEXT: vrgather.vv v8, v16, v24
-; CHECK-NEXT: vadd.vi v24, v24, 1
-; CHECK-NEXT: vrgather.vv v0, v16, v24
-; CHECK-NEXT: vmv4r.v v12, v0
+; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-NEXT: vlseg2e64.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 8 x i64>, ptr %p
%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.experimental.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
@@ -176,10 +157,8 @@ declare {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deint
define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_load_nxv2f16_nxv4f16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv2f16_nxv4f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl1re16.v v9, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v9, 0
-; CHECK-NEXT: vnsrl.wi v9, v9, 16
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 4 x half>, ptr %p
%retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.experimental.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)
@@ -189,10 +168,8 @@ define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_load_nxv2
define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_load_nxv4f16_nxv8f16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv4f16_nxv8f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re16.v v10, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v10, 0
-; CHECK-NEXT: vnsrl.wi v9, v10, 16
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 8 x half>, ptr %p
%retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.experimental.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)
@@ -202,11 +179,8 @@ define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_load_nxv4
define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_load_nxv2f32_nxv4f32(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv2f32_nxv4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl2re32.v v10, (a0)
-; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT: vnsrl.wx v9, v10, a0
-; CHECK-NEXT: vnsrl.wi v8, v10, 0
+; CHECK-NEXT: vlseg2e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 4 x float>, ptr %p
%retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.experimental.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)
@@ -216,10 +190,8 @@ define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_load_nx
define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_load_nxv8f16_nxv16f16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv8f16_nxv16f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re16.v v12, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v8, v12, 0
-; CHECK-NEXT: vnsrl.wi v10, v12, 16
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 16 x half>, ptr %p
%retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.experimental.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)
@@ -229,11 +201,8 @@ define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_load_nxv8
define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_load_nxv4f32_nxv8f32(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv4f32_nxv8f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re32.v v12, (a0)
-; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; CHECK-NEXT: vnsrl.wx v10, v12, a0
-; CHECK-NEXT: vnsrl.wi v8, v12, 0
+; CHECK-NEXT: vlseg2e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 8 x float>, ptr %p
%retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)
@@ -243,14 +212,8 @@ define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_load_nx
define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_load_nxv2f64_nxv4f64(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv2f64_nxv4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl4re64.v v12, (a0)
-; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vid.v v8
-; CHECK-NEXT: vadd.vv v16, v8, v8
-; CHECK-NEXT: vrgather.vv v8, v12, v16
-; CHECK-NEXT: vadd.vi v16, v16, 1
-; CHECK-NEXT: vrgather.vv v20, v12, v16
-; CHECK-NEXT: vmv2r.v v10, v20
+; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-NEXT: vlseg2e64.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <vscale x 4 x double>, ptr %p
%retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)
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