[PATCH] D152726: [RISCV][GlobalISel] Legalize all ALU instructions, excluding w-instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:52
+          .clampScalar(0, XLenLLT, XLenLLT)
+          .libcallFor({s128});
+    }
----------------
Is this libcall tested? There is no s128 libcall for RV32, but s64 should use a libcall on RV64.


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:76
+      .clampScalar(0, XLenLLT, XLenLLT)
+      .maxScalar(1, XLenLLT);
+
----------------
G_CONSTANT should only have 1 type. What does `.maxScalar(1, XLenLLT);` here do?


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:79
+  getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
+      .legalFor({XLenLLT})
+      .clampScalar(0, XLenLLT, XLenLLT)
----------------
How can G_ZEXT/G_SEXT/G_ANYEXT be legal for any types? The source and destination should be different types, and there is only 1 legal type on RISC-V.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152726/new/

https://reviews.llvm.org/D152726