[llvm] ee165cd - [AMDGPU] Eliminate SIMCCodeEmitter and de-virtualise encoding methods.
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 5 02:13:39 PDT 2023
Author: Ivan Kosarev
Date: 2023-07-05T10:13:33+01:00
New Revision: ee165cdb1b8b5dad0c694f751e417968fca032fa
URL: https://github.com/llvm/llvm-project/commit/ee165cdb1b8b5dad0c694f751e417968fca032fa
DIFF: https://github.com/llvm/llvm-project/commit/ee165cdb1b8b5dad0c694f751e417968fca032fa.diff
LOG: [AMDGPU] Eliminate SIMCCodeEmitter and de-virtualise encoding methods.
Simplifies some future changes needed for
<https://github.com/llvm/llvm-project/issues/62629>.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D154337
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h
Removed:
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 653f3172c0ac1b..5e41946988798a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -79,7 +79,7 @@ createAMDGPUAsmPrinterPass(TargetMachine &tm,
}
extern "C" void LLVM_EXTERNAL_VISIBILITY LLVMInitializeAMDGPUAsmPrinter() {
- TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
+ TargetRegistry::RegisterAsmPrinter(getTheR600Target(),
llvm::createR600AsmPrinterPass);
TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
createAMDGPUAsmPrinterPass);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index cf466e810d9189..9276479bb299ee 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -351,7 +351,7 @@ static cl::opt<bool> EnableRewritePartialRegUses(
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
// Register the target
- RegisterTargetMachine<R600TargetMachine> X(getTheAMDGPUTarget());
+ RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
PassRegistry *PR = PassRegistry::getPassRegistry();
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index fffabc95391da4..46c43669424078 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -8877,7 +8877,7 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
/// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser() {
- RegisterMCAsmParser<AMDGPUAsmParser> A(getTheAMDGPUTarget());
+ RegisterMCAsmParser<AMDGPUAsmParser> A(getTheR600Target());
RegisterMCAsmParser<AMDGPUAsmParser> B(getTheGCNTarget());
}
diff --git a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
index 24c9cc2d7dd2f4..a1f8be403c441f 100644
--- a/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
+++ b/llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
@@ -348,9 +348,9 @@ createAMDGPUInstrPostProcess(const MCSubtargetInfo &STI,
/// Extern function to initialize the targets for the AMDGPU backend
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMCA() {
- TargetRegistry::RegisterCustomBehaviour(getTheAMDGPUTarget(),
+ TargetRegistry::RegisterCustomBehaviour(getTheR600Target(),
createAMDGPUCustomBehaviour);
- TargetRegistry::RegisterInstrPostProcess(getTheAMDGPUTarget(),
+ TargetRegistry::RegisterInstrPostProcess(getTheR600Target(),
createAMDGPUInstrPostProcess);
TargetRegistry::RegisterCustomBehaviour(getTheGCNTarget(),
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
deleted file mode 100644
index 93bec8aaadfd44..00000000000000
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ /dev/null
@@ -1,20 +0,0 @@
-//===-- AMDGPUCodeEmitter.cpp - AMDGPU Code Emitter interface -------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-/// \file
-/// CodeEmitter interface for SI codegen.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPUMCCodeEmitter.h"
-
-using namespace llvm;
-
-// pin vtable to this file
-void AMDGPUMCCodeEmitter::anchor() {}
-
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h
deleted file mode 100644
index 200c9b8726e267..00000000000000
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h
+++ /dev/null
@@ -1,68 +0,0 @@
-//===-- AMDGPUCodeEmitter.h - AMDGPU Code Emitter interface -----*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-/// \file
-/// CodeEmitter interface for SI codegen.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
-#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCCODEEMITTER_H
-
-#include "llvm/ADT/APInt.h"
-#include "llvm/MC/MCCodeEmitter.h"
-
-namespace llvm {
-
-class MCInst;
-class MCInstrInfo;
-class MCOperand;
-class MCSubtargetInfo;
-
-class AMDGPUMCCodeEmitter : public MCCodeEmitter {
- virtual void anchor();
-
-protected:
- const MCInstrInfo &MCII;
-
- AMDGPUMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {}
-
-public:
- void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
- APInt &Inst, APInt &Scratch,
- const MCSubtargetInfo &STI) const;
-
- virtual void getMachineOpValue(const MCInst &MI, const MCOperand &MO,
- APInt &Op, SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const = 0;
-
- virtual void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const = 0;
-
- virtual void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const = 0;
-
- virtual void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const = 0;
-
- virtual void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
- APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const = 0;
-
- virtual void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const = 0;
-};
-
-} // End namespace llvm
-
-#endif
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index 8a9fea3c8d260f..a6a01479b5b18a 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -150,8 +150,9 @@ static MCInstrAnalysis *createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info) {
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC() {
TargetRegistry::RegisterMCInstrInfo(getTheGCNTarget(), createAMDGPUMCInstrInfo);
- TargetRegistry::RegisterMCInstrInfo(getTheAMDGPUTarget(), createR600MCInstrInfo);
- for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
+ TargetRegistry::RegisterMCInstrInfo(getTheR600Target(),
+ createR600MCInstrInfo);
+ for (Target *T : {&getTheR600Target(), &getTheGCNTarget()}) {
RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
@@ -163,14 +164,14 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC() {
}
// R600 specific registration
- TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
+ TargetRegistry::RegisterMCCodeEmitter(getTheR600Target(),
createR600MCCodeEmitter);
TargetRegistry::RegisterObjectTargetStreamer(
- getTheAMDGPUTarget(), createAMDGPUObjectTargetStreamer);
+ getTheR600Target(), createAMDGPUObjectTargetStreamer);
// GCN specific registration
TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
- createSIMCCodeEmitter);
+ createAMDGPUMCCodeEmitter);
TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
createAMDGPUAsmTargetStreamer);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
index c2e2563c3989c4..006115ba14fc1c 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
@@ -32,8 +32,8 @@ enum AMDGPUDwarfFlavour : unsigned { Wave64 = 0, Wave32 = 1 };
MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour);
-MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
- MCContext &Ctx);
+MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
+ MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
index 25d5ae4ea0b4da..e99986aaade28d 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt
@@ -4,7 +4,6 @@ add_llvm_component_library(LLVMAMDGPUDesc
AMDGPUELFStreamer.cpp
AMDGPUInstPrinter.cpp
AMDGPUMCAsmInfo.cpp
- AMDGPUMCCodeEmitter.cpp
AMDGPUMCTargetDesc.cpp
AMDGPUTargetStreamer.cpp
R600InstPrinter.cpp
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
index 04808a713cf4d9..e052729dd54668 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -13,7 +13,6 @@
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/AMDGPUFixupKinds.h"
-#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIDefines.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -33,19 +32,13 @@ using namespace llvm;
namespace {
-class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
+class AMDGPUMCCodeEmitter : public MCCodeEmitter {
const MCRegisterInfo &MRI;
-
- /// Encode an fp or int literal
- std::optional<uint32_t> getLitEncoding(const MCOperand &MO,
- const MCOperandInfo &OpInfo,
- const MCSubtargetInfo &STI) const;
+ const MCInstrInfo &MCII;
public:
- SIMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
- : AMDGPUMCCodeEmitter(mcii), MRI(*ctx.getRegisterInfo()) {}
- SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
- SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
+ AMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI)
+ : MRI(MRI), MCII(MCII) {}
/// Encode the instruction and write it to the OS.
void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
@@ -54,29 +47,29 @@ class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
void getMachineOpValue(const MCInst &MI, const MCOperand &MO, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const override;
+ const MCSubtargetInfo &STI) const;
/// Use a fixup to encode the simm16 field for SOPP branch
/// instructions.
void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const override;
+ const MCSubtargetInfo &STI) const;
void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const override;
+ const MCSubtargetInfo &STI) const;
void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const override;
+ const MCSubtargetInfo &STI) const;
void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const override;
+ const MCSubtargetInfo &STI) const;
void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const override;
+ const MCSubtargetInfo &STI) const;
private:
uint64_t getImplicitOpSelHiEncoding(int Opcode) const;
@@ -84,13 +77,22 @@ class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
unsigned OpNo, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+
+ /// Encode an fp or int literal.
+ std::optional<uint32_t> getLitEncoding(const MCOperand &MO,
+ const MCOperandInfo &OpInfo,
+ const MCSubtargetInfo &STI) const;
+
+ void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
+ APInt &Inst, APInt &Scratch,
+ const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
-MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
- MCContext &Ctx) {
- return new SIMCCodeEmitter(MCII, Ctx);
+MCCodeEmitter *llvm::createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
+ MCContext &Ctx) {
+ return new AMDGPUMCCodeEmitter(MCII, *Ctx.getRegisterInfo());
}
// Returns the encoding value to use if the given integer is an integer inline
@@ -220,9 +222,9 @@ static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
}
std::optional<uint32_t>
-SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
- const MCOperandInfo &OpInfo,
- const MCSubtargetInfo &STI) const {
+AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
+ const MCOperandInfo &OpInfo,
+ const MCSubtargetInfo &STI) const {
int64_t Imm;
if (MO.isExpr()) {
const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
@@ -297,7 +299,7 @@ SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
}
}
-uint64_t SIMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
+uint64_t AMDGPUMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
using namespace AMDGPU::VOP3PEncoding;
using namespace AMDGPU::OpName;
@@ -317,10 +319,10 @@ static bool isVCMPX64(const MCInstrDesc &Desc) {
Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC);
}
-void SIMCCodeEmitter::encodeInstruction(const MCInst &MI,
- SmallVectorImpl<char> &CB,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
+ SmallVectorImpl<char> &CB,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
int Opcode = MI.getOpcode();
APInt Encoding, Scratch;
getBinaryCodeForInstr(MI, Fixups, Encoding, Scratch, STI);
@@ -408,10 +410,10 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI,
}
}
-void SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
- APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+void AMDGPUMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
+ APInt &Op,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isExpr()) {
@@ -424,20 +426,19 @@ void SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
}
}
-void SIMCCodeEmitter::getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo,
- APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+void AMDGPUMCCodeEmitter::getSMEMOffsetEncoding(
+ const MCInst &MI, unsigned OpNo, APInt &Op,
+ SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
auto Offset = MI.getOperand(OpNo).getImm();
// VI only supports 20-bit unsigned offsets.
assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));
Op = Offset;
}
-void SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
- APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+void AMDGPUMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
+ APInt &Op,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
using namespace AMDGPU::SDWA;
uint64_t RegEnc = 0;
@@ -465,10 +466,9 @@ void SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
llvm_unreachable("Unsupported operand kind");
}
-void SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
- APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+void AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding(
+ const MCInst &MI, unsigned OpNo, APInt &Op,
+ SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
using namespace AMDGPU::SDWA;
uint64_t RegEnc = 0;
@@ -484,10 +484,9 @@ void SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
Op = RegEnc;
}
-void SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
- APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+void AMDGPUMCCodeEmitter::getAVOperandEncoding(
+ const MCInst &MI, unsigned OpNo, APInt &Op,
+ SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
unsigned Reg = MI.getOperand(OpNo).getReg();
uint64_t Enc = MRI.getEncodingValue(Reg);
@@ -536,10 +535,10 @@ static bool needsPCRel(const MCExpr *Expr) {
llvm_unreachable("invalid kind");
}
-void SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
- const MCOperand &MO, APInt &Op,
- SmallVectorImpl<MCFixup> &Fixups,
- const MCSubtargetInfo &STI) const {
+void AMDGPUMCCodeEmitter::getMachineOpValue(const MCInst &MI,
+ const MCOperand &MO, APInt &Op,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
if (MO.isReg()){
Op = MRI.getEncodingValue(MO.getReg());
return;
@@ -548,7 +547,7 @@ void SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
}
-void SIMCCodeEmitter::getMachineOpValueCommon(
+void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
diff --git a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
index 7573af59705658..98fd16e59bf1f5 100644
--- a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp
@@ -15,13 +15,13 @@
using namespace llvm;
-/// The target which supports all AMD GPUs. This will eventually
-/// be deprecated and there will be a R600 target and a GCN target.
-Target &llvm::getTheAMDGPUTarget() {
+/// The target for R600 GPUs.
+Target &llvm::getTheR600Target() {
static Target TheAMDGPUTarget;
return TheAMDGPUTarget;
}
-/// The target for GCN GPUs
+
+/// The target for GCN GPUs.
Target &llvm::getTheGCNTarget() {
static Target TheGCNTarget;
return TheGCNTarget;
@@ -29,7 +29,7 @@ Target &llvm::getTheGCNTarget() {
/// Extern function to initialize the targets for the AMDGPU backend
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetInfo() {
- RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600",
+ RegisterTarget<Triple::r600, false> R600(getTheR600Target(), "r600",
"AMD GPUs HD2XXX-HD6XXX", "AMDGPU");
RegisterTarget<Triple::amdgcn, false> GCN(getTheGCNTarget(), "amdgcn",
"AMD GCN GPUs", "AMDGPU");
diff --git a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h
index 1e6dbd90b0c1eb..45470167a33131 100644
--- a/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h
+++ b/llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h
@@ -17,11 +17,10 @@ namespace llvm {
class Target;
-/// The target which supports all AMD GPUs. This will eventually
-/// be deprecated and there will be a R600 target and a GCN target.
-Target &getTheAMDGPUTarget();
+/// The target for R600 GPUs.
+Target &getTheR600Target();
-/// The target for GCN GPUs
+/// The target for GCN GPUs.
Target &getTheGCNTarget();
}
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