[PATCH] D154470: [AMDGPU] Fix ISD perm compute known bits wrong.

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 created this revision.
bcl5980 added reviewers: foad, arsenm, rampitec.
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SelBits can be 7.


https://reviews.llvm.org/D154470

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp


Index: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5016,7 +5016,7 @@
         SelBits *= 8;
         Known.One |= ((RHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
         Known.Zero |= ((RHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
-      } else if (SelBits < 7) {
+      } else if (SelBits < 8) {
         SelBits = (SelBits & 3) * 8;
         Known.One |= ((LHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
         Known.Zero |= ((LHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;


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