[PATCH] D154412: [RISCV] Add support for XCVbi extension in CV32E40P

[Funan Zeng via Phabricator via llvm-commits]

melonedo updated this revision to Diff 537199.
melonedo added a comment.

Adopt suggestions

Rename CV to RV; fix indentation and line wrapping; add CORE-V to feature description.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154412/new/

https://reviews.llvm.org/D154412

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
  llvm/test/MC/RISCV/corev/XCVbi-invalid.s
  llvm/test/MC/RISCV/corev/XCVbi.s

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