[PATCH] D154193: [X86]Remove TEST in AND32ri+TEST16rr in peephole-opt

[Wang, Xin via Phabricator via llvm-commits]

XinWang10 added inline comments.


================
Comment at: llvm/lib/Target/X86/X86InstrInfo.cpp:1007
+           VregDefInstr->getOpcode() == X86::AND64ri32) &&
+          isInt<16>(VregDefInstr->getOperand(2).getImm())))
+      return false;
----------------
craig.topper wrote:
> XinWang10 wrote:
> > craig.topper wrote:
> > > Doesn't it need to be isUint<16>?
> > > 
> > > Bit 15 would also need to be 0 if the sign flag is being used.
> > Yes, It should be.
> Do we have a test where we use the sign flag? The AND would set the sign flag based on bit 31. the TEST16rr would set the sign flag based on bit 15. So we could only do the transform if bit 31 and bit 15 are known to be zero (bit 31 is handled by the isUint<16> check. Or we need to not be using the sign flag from the test.
I would add a test for it. It will be the same as the original logic for test64rr since the following code, if user use sf we will disable the removal.


Repository:
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  https://reviews.llvm.org/D154193/new/

https://reviews.llvm.org/D154193