[PATCH] D143762: [AMDGPU] Enable whole wave register copy

Tue Jul 4 04:19:38 PDT 2023

yassingh added a comment.

In D143762#4456567 <https://reviews.llvm.org/D143762#4456567>, @arsenm wrote:

> Also not sure how this has no test changes

This patch was originally submitted with 0 tests. My understating is we won't see any effects of these changes until WWM copies are inserted in code by the next patch(Spill SGPRs to virtual VGPRs).
cc @cdevadas

================
Comment at: llvm/test/CodeGen/AMDGPU/llc-pipeline.ll:368
 ; GCN-O1-NEXT:        Greedy Register Allocator
+; GCN-O1-NEXT:        SI Lower WWM Copies
 ; GCN-O1-NEXT:        GCN NSA Reassign
----------------
arsenm wrote:
> I think I lost track of what was going on with -O0, did this lose the -O0 run?
It was introduced when we moved from PRED_COPY "simplification" to proper lowering mechanism. Was removed again after the approach changed back to lowering WWM_COPY to COPY first. I have added the O0 invocation back but it's not doing anything.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D143762/new/

https://reviews.llvm.org/D143762