[PATCH] D154193: [X86]Remove TEST in AND32ri+TEST16rr in peephole-opt

[Wang, Xin via Phabricator via llvm-commits]

XinWang10 added inline comments.


================
Comment at: llvm/lib/Target/X86/X86InstrInfo.cpp:1007
+           VregDefInstr->getOpcode() == X86::AND64ri32) &&
+          isInt<16>(VregDefInstr->getOperand(2).getImm())))
+      return false;
----------------
craig.topper wrote:
> Doesn't it need to be isUint<16>?
> 
> Bit 15 would also need to be 0 if the sign flag is being used.
Yes, It should be.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154193/new/

https://reviews.llvm.org/D154193