[PATCH] D153748: [RISCV] Add support for XCValu extension in CV32E40P

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

You might need to add extension in `RISCVISAInfo.cpp` for -march support?



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Comment at: llvm/docs/RISCVUsage.rst:278
+``XCValu``
+  LLVM implements `version 1.3.1 of the Core-V ALU custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.mac.` as described in the specification. These instructions are only available for riscv32 at this time.
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@jeremybennett say it's 1.0 here?

https://github.com/riscv-non-isa/riscv-toolchain-conventions/blob/master/README.mkd#list-of-vendor-extensions


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