[llvm] 86829d1 - [CSKY] Optimize IR pattern icmp-select with DECT32/DECF32
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 3 00:04:06 PDT 2023
Author: Ben Shi
Date: 2023-07-03T15:03:43+08:00
New Revision: 86829d15f4ca62e70e690a9414eb0dfd470bd393
URL: https://github.com/llvm/llvm-project/commit/86829d15f4ca62e70e690a9414eb0dfd470bd393
DIFF: https://github.com/llvm/llvm-project/commit/86829d15f4ca62e70e690a9414eb0dfd470bd393.diff
LOG: [CSKY] Optimize IR pattern icmp-select with DECT32/DECF32
Reviewed By: zixuan-wu
Differential Revision: https://reviews.llvm.org/D153518
Added:
Modified:
llvm/lib/Target/CSKY/CSKYInstrInfo.td
llvm/test/CodeGen/CSKY/dect-decf.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index 8024d4a7b8e5b3..8f19de81ac81cc 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -120,6 +120,10 @@ class uimm<int num, int shift = 0> : Operand<i32>,
let DecoderMethod = "decodeUImmOperand<"#num#", "#shift#">";
}
+class uimm_neg<int num, int shift = 0> : Operand<i32>,
+ ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(-Imm);"> {
+}
+
class simm<int num, int shift = 0> : Operand<i32>,
ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {
let EncoderMethod = "getImmOpValue<"#shift#">";
@@ -396,6 +400,8 @@ def uimm20 : uimm<20>;
def uimm24 : uimm<24>;
def uimm24_8 : uimm<24, 8>;
+def uimm5_neg : uimm_neg<5>;
+
def simm8_2 : simm<8, 2>;
class RegSeqAsmOperand<string Suffix = ""> : AsmOperandClass {
@@ -1257,8 +1263,14 @@ def : Pat<(select (i32 (setne GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5:$imm)
(INCT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
def : Pat<(select (i32 (seteq GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),
(INCF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
-
-multiclass INCTF32Pat0<PatFrag cond0, PatFrag cond1, Instruction cmp> {
+def : Pat<(select (i32 (setne GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false),
+ (DECT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+def : Pat<(select (i32 (seteq GPR:$rs1, uimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false),
+ (DECF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$false, GPR:$rx,
+ (imm_neg_XFORM uimm5:$imm))>;
+
+multiclass INCDECPat<PatFrag cond0, PatFrag cond1, Instruction cmp> {
def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),
(INCT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),
@@ -1267,19 +1279,40 @@ multiclass INCTF32Pat0<PatFrag cond0, PatFrag cond1, Instruction cmp> {
(INCF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),
(INCT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
-}
-
-defm : INCTF32Pat0<setuge, setult, CMPHSI32>;
-defm : INCTF32Pat0<setlt, setge, CMPLTI32>;
-
-def : Pat<(select CARRY:$ca, (add GPR:$rx, uimm5:$imm), GPR:$false),
- (INCT32 CARRY:$ca, GPR:$false, GPR:$rx, uimm5:$imm)>;
-def : Pat<(select CARRY:$ca, GPR:$true, (add GPR:$rx, uimm5:$imm)),
- (INCF32 CARRY:$ca, GPR:$true, GPR:$rx, uimm5:$imm)>;
-def : Pat<(select (and CARRY:$ca, 1), (add GPR:$rx, uimm5:$imm), GPR:$false),
- (INCT32 CARRY:$ca, GPR:$false, GPR:$rx, uimm5:$imm)>;
-def : Pat<(select (and CARRY:$ca, 1), GPR:$true, (add GPR:$rx, uimm5:$imm)),
- (INCF32 CARRY:$ca, GPR:$true, GPR:$rx, uimm5:$imm)>;
+ def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),
+ (DECT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+ def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),
+ (DECF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+ def : Pat<(select (i32 (cond0 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),
+ (DECF32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+ def : Pat<(select (i32 (cond1 GPR:$rs1, oimm16:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),
+ (DECT32 (cmp GPR:$rs1, oimm16:$rs2), GPR:$other, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+}
+
+defm : INCDECPat<setuge, setult, CMPHSI32>;
+defm : INCDECPat<setlt, setge, CMPLTI32>;
+
+def : Pat<(select CARRY:$ca, (add GPR:$rx, uimm5:$imm), GPR:$other),
+ (INCT32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>;
+def : Pat<(select CARRY:$ca, GPR:$other, (add GPR:$rx, uimm5:$imm)),
+ (INCF32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>;
+def : Pat<(select (and CARRY:$ca, 1), (add GPR:$rx, uimm5:$imm), GPR:$other),
+ (INCT32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>;
+def : Pat<(select (and CARRY:$ca, 1), GPR:$other, (add GPR:$rx, uimm5:$imm)),
+ (INCF32 CARRY:$ca, GPR:$other, GPR:$rx, uimm5:$imm)>;
+
+def : Pat<(select CARRY:$ca, (add GPR:$rx, uimm5_neg:$imm), GPR:$other),
+ (DECT32 CARRY:$ca, GPR:$other, GPR:$rx, (imm_neg_XFORM uimm5_neg:$imm))>;
+def : Pat<(select CARRY:$ca, GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),
+ (DECF32 CARRY:$ca, GPR:$other, GPR:$rx, (imm_neg_XFORM uimm5_neg:$imm))>;
+def : Pat<(select (and CARRY:$ca, 1), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),
+ (DECT32 CARRY:$ca, GPR:$other, GPR:$rx, (imm_neg_XFORM uimm5_neg:$imm))>;
+def : Pat<(select (and CARRY:$ca, 1), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),
+ (DECF32 CARRY:$ca, GPR:$other, GPR:$rx, (imm_neg_XFORM uimm5_neg:$imm))>;
def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
(MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>;
@@ -1309,23 +1342,48 @@ def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), G
(INCT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),
(INCF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
-
-multiclass INCTF32Pat1<PatFrag cond0, PatFrag cond1, Instruction cmp, Instruction incdec0,
- Instruction incdec1> {
+def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false),
+ (DECT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false),
+ (DECF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+
+multiclass INCPat<PatFrag cond0, PatFrag cond1, Instruction cmp, Instruction inc0, Instruction inc1> {
def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),
- (incdec0 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
+ (inc0 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),
- (incdec1 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
+ (inc1 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx, uimm5:$imm)>;
def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$other),
- (incdec0 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>;
+ (inc0 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>;
def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5:$imm)),
- (incdec1 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>;
-}
-
-defm : INCTF32Pat1<setuge, setule, CMPHS32, INCT32, INCF32>;
-defm : INCTF32Pat1<setult, setugt, CMPHS32, INCF32, INCT32>;
-defm : INCTF32Pat1<setlt, setgt, CMPLT32, INCT32, INCF32>;
-defm : INCTF32Pat1<setge, setle, CMPLT32, INCF32, INCT32>;
+ (inc1 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx, uimm5:$imm)>;
+}
+
+defm : INCPat<setuge, setule, CMPHS32, INCT32, INCF32>;
+defm : INCPat<setult, setugt, CMPHS32, INCF32, INCT32>;
+defm : INCPat<setlt, setgt, CMPLT32, INCT32, INCF32>;
+defm : INCPat<setge, setle, CMPLT32, INCF32, INCT32>;
+
+multiclass DECPat<PatFrag cond0, PatFrag cond1, Instruction cmp, Instruction dec0, Instruction dec1> {
+ def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),
+ (dec0 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+ def : Pat<(select (i32 (cond0 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),
+ (dec1 (cmp GPR:$rs1, GPR:$rs2), GPR:$other, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+ def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$other),
+ (dec0 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+ def : Pat<(select (i32 (cond1 GPR:$rs1, GPR:$rs2)), GPR:$other, (add GPR:$rx, uimm5_neg:$imm)),
+ (dec1 (cmp GPR:$rs2, GPR:$rs1), GPR:$other, GPR:$rx,
+ (imm_neg_XFORM uimm5_neg:$imm))>;
+}
+
+defm : DECPat<setuge, setule, CMPHS32, DECT32, DECF32>;
+defm : DECPat<setult, setugt, CMPHS32, DECF32, DECT32>;
+defm : DECPat<setlt, setgt, CMPLT32, DECT32, DECF32>;
+defm : DECPat<setge, setle, CMPLT32, DECF32, DECT32>;
def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
(MOVT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
diff --git a/llvm/test/CodeGen/CSKY/dect-decf.ll b/llvm/test/CodeGen/CSKY/dect-decf.ll
index fb3f1a52776f86..7bb5f6cedd3071 100644
--- a/llvm/test/CodeGen/CSKY/dect-decf.ll
+++ b/llvm/test/CodeGen/CSKY/dect-decf.ll
@@ -4,9 +4,8 @@
define i32 @select_by_icmp_ugt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_ugt:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmphs16 a1, a0
-; CHECK-NEXT: movf32 a3, a2
+; CHECK-NEXT: decf32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp ugt i32 %t0, %t1
@@ -18,9 +17,8 @@ define i32 @select_by_icmp_ugt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_sgt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_sgt:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmplt16 a1, a0
-; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: dect32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp sgt i32 %t0, %t1
@@ -32,9 +30,8 @@ define i32 @select_by_icmp_sgt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_uge(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_uge:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmphs16 a0, a1
-; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: dect32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp uge i32 %t0, %t1
@@ -46,9 +43,8 @@ define i32 @select_by_icmp_uge(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_sge(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_sge:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmplt16 a0, a1
-; CHECK-NEXT: movf32 a3, a2
+; CHECK-NEXT: decf32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp sge i32 %t0, %t1
@@ -60,9 +56,8 @@ define i32 @select_by_icmp_sge(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_ult(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_ult:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmphs16 a0, a1
-; CHECK-NEXT: movf32 a3, a2
+; CHECK-NEXT: decf32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp ult i32 %t0, %t1
@@ -74,9 +69,8 @@ define i32 @select_by_icmp_ult(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_slt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_slt:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmplt16 a0, a1
-; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: dect32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp slt i32 %t0, %t1
@@ -88,9 +82,8 @@ define i32 @select_by_icmp_slt(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_ule(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_ule:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmphs16 a1, a0
-; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: dect32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp ule i32 %t0, %t1
@@ -102,9 +95,8 @@ define i32 @select_by_icmp_ule(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_sle(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_sle:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmplt16 a1, a0
-; CHECK-NEXT: movf32 a3, a2
+; CHECK-NEXT: decf32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp sle i32 %t0, %t1
@@ -116,9 +108,8 @@ define i32 @select_by_icmp_sle(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_ne(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_ne:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmpne16 a0, a1
-; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: dect32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp ne i32 %t0, %t1
@@ -130,9 +121,8 @@ define i32 @select_by_icmp_ne(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_eq(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_eq:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a2, 10
; CHECK-NEXT: cmpne16 a0, a1
-; CHECK-NEXT: movf32 a3, a2
+; CHECK-NEXT: decf32 a3, a2, 10
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
%t4 = icmp eq i32 %t0, %t1
@@ -144,10 +134,9 @@ define i32 @select_by_icmp_eq(i32 %t0, i32 %t1, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_ugt_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_ugt_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: movi16 a3, 128
; CHECK-NEXT: cmphs16 a3, a0
-; CHECK-NEXT: movf32 a2, a1
+; CHECK-NEXT: decf32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp ugt i32 %t0, 128
@@ -159,10 +148,9 @@ define i32 @select_by_icmp_ugt_imm(i32 %t0, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_sgt_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_sgt_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: movi16 a3, 128
; CHECK-NEXT: cmplt16 a3, a0
-; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: dect32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp sgt i32 %t0, 128
@@ -174,10 +162,9 @@ define i32 @select_by_icmp_sgt_imm(i32 %t0, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_uge_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_uge_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: movi16 a3, 127
; CHECK-NEXT: cmphs16 a3, a0
-; CHECK-NEXT: movf32 a2, a1
+; CHECK-NEXT: decf32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp uge i32 %t0, 128
@@ -189,10 +176,9 @@ define i32 @select_by_icmp_uge_imm(i32 %t0, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_sge_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_sge_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: movi16 a3, 127
; CHECK-NEXT: cmplt16 a3, a0
-; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: dect32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp sge i32 %t0, 128
@@ -204,9 +190,8 @@ define i32 @select_by_icmp_sge_imm(i32 %t0, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_ult_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_ult_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: cmphsi32 a0, 128
-; CHECK-NEXT: movf32 a2, a1
+; CHECK-NEXT: decf32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp ult i32 %t0, 128
@@ -218,9 +203,8 @@ define i32 @select_by_icmp_ult_imm(i32 %t0, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_slt_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_slt_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: cmplti32 a0, 128
-; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: dect32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp slt i32 %t0, 128
@@ -232,9 +216,8 @@ define i32 @select_by_icmp_slt_imm(i32 %t0, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_ule_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_ule_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: cmphsi32 a0, 129
-; CHECK-NEXT: movf32 a2, a1
+; CHECK-NEXT: decf32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp ule i32 %t0, 128
@@ -246,9 +229,8 @@ define i32 @select_by_icmp_ule_imm(i32 %t0, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_sle_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_sle_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: cmplti32 a0, 129
-; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: dect32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp sle i32 %t0, 128
@@ -260,9 +242,8 @@ define i32 @select_by_icmp_sle_imm(i32 %t0, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_ne_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_ne_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: cmpnei32 a0, 128
-; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: dect32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp ne i32 %t0, 128
@@ -274,9 +255,8 @@ define i32 @select_by_icmp_ne_imm(i32 %t0, i32 %t2, i32 %t3) {
define i32 @select_by_icmp_eq_imm(i32 %t0, i32 %t2, i32 %t3) {
; CHECK-LABEL: select_by_icmp_eq_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: subi16 a1, 10
; CHECK-NEXT: cmpnei32 a0, 128
-; CHECK-NEXT: movf32 a2, a1
+; CHECK-NEXT: decf32 a2, a1, 10
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
%t4 = icmp eq i32 %t0, 128
@@ -300,9 +280,8 @@ define i32 @select_by_call_t(i32 %t0, i32 %t1, i32 %t2) {
; CHECK-NEXT: mov16 l0, a2
; CHECK-NEXT: mov16 l1, a1
; CHECK-NEXT: jsri32 [.LCPI20_0]
-; CHECK-NEXT: subi32 a1, l1, 10
; CHECK-NEXT: btsti16 a0, 0
-; CHECK-NEXT: movt32 l0, a1
+; CHECK-NEXT: dect32 l0, l1, 10
; CHECK-NEXT: mov16 a0, l0
; CHECK-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
; CHECK-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
@@ -335,10 +314,9 @@ define i32 @select_by_call_f(i32 %t0, i32 %t1, i32 %t2) {
; CHECK-NEXT: mov16 l0, a2
; CHECK-NEXT: mov16 l1, a1
; CHECK-NEXT: jsri32 [.LCPI21_0]
-; CHECK-NEXT: subi32 a1, l1, 10
; CHECK-NEXT: btsti16 a0, 0
-; CHECK-NEXT: movt32 a1, l0
-; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: decf32 l0, l1, 10
+; CHECK-NEXT: mov16 a0, l0
; CHECK-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
; CHECK-NEXT: ld16.w l0, (sp, 4) # 4-byte Folded Reload
; CHECK-NEXT: ld16.w l1, (sp, 8) # 4-byte Folded Reload
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