[PATCH] D153607: [CSKY] Optimize conditional branch

[Ben Shi via Phabricator via llvm-commits]

benshi001 added a comment.

In D153607#4467587 <https://reviews.llvm.org/D153607#4467587>, @barannikov88 wrote:

> In D153607#4462927 <https://reviews.llvm.org/D153607#4462927>, @benshi001 wrote:
>
>> In D153607#4462762 <https://reviews.llvm.org/D153607#4462762>, @zixuan-wu wrote:
>>
>>> need more case about bhz/bhsz?
>>
>> It is hard to add tests for
>>
>>   def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 1))), bb:$imm16),
>>             (BHZ32 GPR:$rs1, bb:$imm16)>;
>>
>> Since the original IR pattern
>>
>>   %icmp = icmp sge i32 %x, 1
>>   br i1 %icmp, label %label1, label %label2
>>
>> is always transformed to an equivalent form by DAGCombiner
>>
>>   %icmp = icmp slt i32 %x, 1
>>   br i1 %icmp, label %label2, label %label1
>>
>> before reaching to the CSKY backend.
>>
>> And `BHSZ32` has the same issue.
>>
>> I add these two `Pat`s for `BHSZ32` and `BHZ32`, just in case there is future changes in the DAGCombiner.
>
> Try something like:
>
>   extern void on_false(void);
>   void test_ge_1(int x) {
>     if (!(x >= 1))
>       on_false();
>   }

Unfortunately your program can not lead to `BHSZ` or `BHZ`, still `BLSZ` as follow,

          .type   test_ge_1, at function
  test_ge_1:                              # @test_ge_1
  # %bb.0:
          subi16  sp, sp, 4
          st32.w  lr, (sp, 0)                     # 4-byte Folded Spill
          blsz32  a0, .LBB0_2
  # %bb.1:
          ld32.w  lr, (sp, 0)                     # 4-byte Folded Reload
          addi16  sp, sp, 4
          rts16
  .LBB0_2:
          jsri32  [.LCPI0_0]
          ld32.w  lr, (sp, 0)                     # 4-byte Folded Reload
          addi16  sp, sp, 4
          rts16
          .p2align        1
  # %bb.3:
          .p2align        2, 0x0
  .LCPI0_0:
          .long   on_false
  .Lfunc_end0:
          .size   test_ge_1, .Lfunc_end0-test_ge_1
                                          # -- End function


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