[PATCH] D154124: [WebAssembly] Fix incorrect assertion in SIMD reduction codegen

[Thomas Lively via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4f065fcb5779: [WebAssembly] Fix incorrect assertion in SIMD reduction codegen (authored by tlively).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154124/new/

https://reviews.llvm.org/D154124

Files:
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll

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