[PATCH] D154234: [RISCV] Fix vfwcvt/vfncvt pseudos w/ rounding mode lowering

[Luke Lau via Phabricator via llvm-commits]

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Some signed opcodes were being lowered to their unsigned counterparts and
vice-versa.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154234

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll

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