[PATCH] D154225: [X86] Enable the VR512 register class when AVX512 is enabled

[Phoebe Wang via Phabricator via llvm-commits]

pengfei requested changes to this revision.
pengfei added a comment.
This revision now requires changes to proceed.

I think this is not the right fix. We intended to define legal types under `useAVX512Regs`.
I think a proper fix should be setting `"min-legal-vector-width"="512"` when parsing the inline asembly in FE.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154225/new/

https://reviews.llvm.org/D154225