[PATCH] D154084: [AArch64] Modify SVE Pseudo appends

[harvin iriawan via Phabricator via llvm-commits]

harviniriawan created this revision.
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- Make Pseudo SVE instructions (e.g. ones with UNDEF, ZERO, or PSEUDO) to append the qualification at the end of instruction opcode
- Ensure that pseudo SVE instructions have the same latency as the actual generated instruction, as this information is used in Machine Scheduling
- Modify cortex-a510 .td file accordingly based on the test
- Modify Neoverse-N2 .td file accordingly


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154084

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedA510.td
  llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/unittests/Target/AArch64/AArch64SvePseudoTest.cpp
  llvm/unittests/Target/AArch64/CMakeLists.txt

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