[PATCH] D153899: [RISCV] Remove legacy TA/TU pseudo distinction for unary instructions

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3426
 // Transform (VMERGE_VVM_<LMUL>_TU false, false, true, allones, vl, sew) to
 // (MMV_V_V_<LMUL>_TU false, true, vl, sew). It may decrease uses of VMSET.
 bool RISCVDAGToDAGISel::performVMergeToVMv(SDNode *N) {
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craig.topper wrote:
> While you're here, can you fix this typo. `MMV`->`VMV`
Fixed in 49428ba.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir:778
   ; CHECK-NEXT:   [[PHI2:%[0-9]+]]:vr = PHI [[COPY3]], %bb.0, %16, %bb.1
+  ; CHECK-NEXT:   dead $x0 = PseudoVSETVLIX0 killed $x0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
   ; CHECK-NEXT:   [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[PHI]], 4, 5 /* e32 */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4)
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craig.topper wrote:
> What happened here?
It looks my hand update to the MIR was wrong.  The undef form is post register allocation, I should have used an implicit_def instruction here.  Same problem in vsetvli-insert.mir.

Thanks for catching this.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D153899/new/

https://reviews.llvm.org/D153899