[PATCH] D153864: [RISCV] Lower interleave2 intrinsics to vsseg2

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:16912
+                                           {InVTy, XLenTy});
+    VL = ConstantInt::get(XLenTy, RISCV::VLMaxSentinel);
+  }
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While VLMaxSentinel happens to be -1, I think that was more of a contract between isel and RISCVInsertVSETVLI for the MachineOperand. Should probably just use Constant::getAllOnes here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153864/new/

https://reviews.llvm.org/D153864