[PATCH] D153879: [AMDGPU] Handle Additional Cases in tryFoldPhiAGPR

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp:1644
 }
 
+static bool isAGPRCopy(const SIRegisterInfo &TRI,
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Doc comment


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Comment at: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp:1647
+                       const MachineRegisterInfo &MRI, const MachineInstr &Copy,
+                       Register &OutReg, unsigned &OutSubRegMask) {
+  assert(Copy.isCopy());
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Don't call it SubRegMask, it's just the SubReg


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Comment at: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp:1667
+  const MachineInstr *CopySrcDef = MRI.getVRegDef(CopySrcReg);
+  if (!CopySrcDef || !CopySrcDef->isCopy())
+    return false;
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We really ought to ban defless registers in SSA but you do need this for undef sources


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Comment at: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp:1762
+        Register AGPRSrc;
+        unsigned AGPRRegMask = AMDGPU::NoSubRegister;
+        if (isAGPRCopy(*TRI, *MRI, *Def, AGPRSrc, AGPRRegMask)) {
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It's not a regmask, it's just a subreg index


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Comment at: llvm/test/CodeGen/AMDGPU/fold-agpr-phis.mir:505
+  bb.2:
+    S_ENDPGM 0
+...
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Could also use and end to end IR test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153879/new/

https://reviews.llvm.org/D153879