[PATCH] D153847: [AArch64] Remove vector shift instrinsic with shift amount zero

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/arm64-vshift.ll:3491
+
+define void @sqshlu_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {
+; CHECK-LABEL: sqshlu_zero_shift_amount:
----------------
dmgreen wrote:
> Apparently this one is not correct, as the sqshlu will round the input even with a zero shift. The others look OK.
Ah... I did not know that.
If possible, can you let me know where I can find that the `sqshlu` will round the input even with a zero shift please?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153847/new/

https://reviews.llvm.org/D153847