[PATCH] D153847: [AArch64] Remove vector shift instrinsic with shift amount zero

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks - looks mostly good to me. Like I said before, there might be some advantage to doing this in instcombine in order to doing the transform earlier, but this will be useful in DAG too.



================
Comment at: llvm/test/CodeGen/AArch64/arm64-vshift.ll:3491
+
+define void @sqshlu_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {
+; CHECK-LABEL: sqshlu_zero_shift_amount:
----------------
Apparently this one is not correct, as the sqshlu will round the input even with a zero shift. The others look OK.


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  https://reviews.llvm.org/D153847/new/

https://reviews.llvm.org/D153847