[PATCH] D153763: [ARM] in ExpandTMOV32BitImm, CPSR register ops should be `Define`d

[Ties Stuij via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG03db28edbb71: [ARM] in ExpandTMOV32BitImm, CPSR register ops should be `Define`d (authored by stuij).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153763/new/

https://reviews.llvm.org/D153763

Files:
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/test/CodeGen/ARM/execute-only.ll


Index: llvm/test/CodeGen/ARM/execute-only.ll
===================================================================
--- llvm/test/CodeGen/ARM/execute-only.ll
+++ llvm/test/CodeGen/ARM/execute-only.ll
@@ -1,5 +1,3 @@
-; UNSUPPORTED: expensive_checks
-
 ; RUN: llc -mtriple=thumbv8m.base-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv8m.base-eabi -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
 ; RUN: llc -mtriple=thumbv7m-eabi      -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
Index: llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -984,18 +984,18 @@
 
   Upper8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tMOVi8), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill);
+          .add(t1CondCodeOp(true));
 
   LSL_U8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill)
+          .add(t1CondCodeOp(true))
           .addReg(DstReg)
           .addImm(8)
           .add(predOps(ARMCC::AL))
           .setMIFlags(MIFlags);
 
   Upper0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
-                 .addReg(ARM::CPSR, RegState::Kill)
+                 .add(t1CondCodeOp(true))
                  .addReg(DstReg);
 
   MachineInstr *LSL_U0_7 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
@@ -1003,7 +1003,7 @@
 
   Lower8_15 =
       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8), DstReg)
-          .addReg(ARM::CPSR, RegState::Kill)
+          .add(t1CondCodeOp(true))
           .addReg(DstReg);
 
   MachineInstr *LSL_L8_15 = MBB.getParent()->CloneMachineInstr(LSL_U8_15);
@@ -1011,7 +1011,7 @@
 
   Lower0_7 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tADDi8))
                  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-                 .addReg(ARM::CPSR, RegState::Kill)
+                 .add(t1CondCodeOp(true))
                  .addReg(DstReg);
 
   Upper8_15.setMIFlags(MIFlags);


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