[PATCH] D151449: [RISCV] Add DAG combine for CTTZ/CTLZ in the case of input 0

[Mikhail Gudim via Phabricator via llvm-commits]

mgudim added a comment.

@djtodoro Thanks for working on this. LGTM, given that you fix the tests. I would feel more comfortable if someone else (@asb, @craig.topper, @reames) gave a final approval.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11429
+  SDValue CTZ;
+
+  SDValue ValOnZero;
----------------
Suggestion: I would use `Count` or `CountZeroes`. On ARM `CTZ` means `CTTZ`.


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https://reviews.llvm.org/D151449