[PATCH] D143762: [AMDGPU] Enable whole wave register copy

Christudasan Devadasan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 27 06:14:54 PDT 2023


cdevadas added a comment.

Remove the test llvm/test/CodeGen/AMDGPU/skip-subreg-copy-from-iswwmcopy-check.mir. It is no longer needed as you have dropped `isWWMCopy` function.



================
Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1974
-  virtual unsigned
-  getLiveRangeSplitOpcode(Register reg, const MachineRegisterInfo &MRI) const {
     return TargetOpcode::COPY;
----------------
Did you rebase this patch after the prototype change in D150388?
This diff shouldn't be here.


================
Comment at: llvm/lib/CodeGen/SplitKit.cpp:539
     MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
-  const MCInstrDesc &Desc = TII.get(TII.getLiveRangeSplitOpcode(FromReg, MRI));
   SlotIndexes &Indexes = *LIS.getSlotIndexes();
----------------
Ditto


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:2419
+SIInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
+  if (MI.getOpcode() == AMDGPU::COPY || MI.getOpcode() == AMDGPU::WWM_COPY)
+    return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
----------------
Still see the regular COPY here.


================
Comment at: llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp:93
+                                             Register Reg) {
+  if (!VRM || Reg.isPhysical())
+    return;
----------------
Remove the VRM check here. We no longer include this pass in the O0 pipeline.


================
Comment at: llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp:125
+      assert(TII->isVGPRCopy(MI));
+      assert(MI.getOperand(0).getReg().isVirtual());
+
----------------
I think this assertion is redundant. We are inserting WWM_COPY only during the live range split.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D143762/new/

https://reviews.llvm.org/D143762



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