[PATCH] D144175: [RISCV] Combine (store/load interleave, deinterleave) into vsseg2/vlseg2

[Luke Lau via Phabricator via llvm-commits]

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Trying to do this as a combine is tricky, as we need to somehow combine it before the vector_interleave/vector_deinterleave ops are legalised, but after the types are legalised. I'm going to rework this to use the `lowerInterleaveIntrinsicToStore`/`lowerDeinterleaveIntrinsicToLoad` target lowering hooks introduced in D146218 <https://reviews.llvm.org/D146218> instead.


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https://reviews.llvm.org/D144175