[PATCH] D153499: [RISCV] Add support for custom CSRs for Sifive S76.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSystemOperands.td:43
 
 def SysRegsList : GenericTable {
   let FilterClass = "SysReg";
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I wonder if maybe we should have a separate table for alternate registers?


Repository:
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  https://reviews.llvm.org/D153499/new/

https://reviews.llvm.org/D153499