[llvm] 09a3585 - [RISCV] Rename all TA variants of VPseudoUnaryMask and VPatoUnaryMask [NFC]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 26 08:33:55 PDT 2023
Author: Philip Reames
Date: 2023-06-26T08:33:42-07:00
New Revision: 09a3585ee95f2eea09f3422427c9bd05183f17dc
URL: https://github.com/llvm/llvm-project/commit/09a3585ee95f2eea09f3422427c9bd05183f17dc
DIFF: https://github.com/llvm/llvm-project/commit/09a3585ee95f2eea09f3422427c9bd05183f17dc.diff
LOG: [RISCV] Rename all TA variants of VPseudoUnaryMask and VPatoUnaryMask [NFC]
All of the these pseudo's take their policy from the policy operand via the normal mechanisms, and aren't "tail agnostic" in any particular sense.
Note that the existing VPatUnaryMask class was unused, and thus this is just a rename.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 9b86ce5967843..24e3929896e62 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1068,7 +1068,7 @@ class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
let UsesMaskPolicy = 1;
}
-class VPseudoUnaryMaskTA_NoExcept<VReg RetClass, VReg OpClass, string Constraint = ""> :
+class VPseudoUnaryMask_NoExcept<VReg RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, VMaskOp:$vm,
AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
@@ -1083,7 +1083,7 @@ class VPseudoUnaryMaskTA_NoExcept<VReg RetClass, VReg OpClass, string Constraint
let usesCustomInserter = 1;
}
-class VPseudoUnaryMaskTA_FRM<VReg RetClass, VReg OpClass, string Constraint = ""> :
+class VPseudoUnaryMask_FRM<VReg RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$frm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
@@ -3568,8 +3568,8 @@ multiclass VPseudoConversionRM<VReg RetClass,
LMULInfo MInfo,
string Constraint = ""> {
let VLMul = MInfo.value in {
- def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA_FRM<RetClass, Op1Class,
- Constraint>;
+ def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
+ Constraint>;
}
}
@@ -3578,7 +3578,7 @@ multiclass VPseudoConversionNoExcept<VReg RetClass,
LMULInfo MInfo,
string Constraint = ""> {
let VLMul = MInfo.value in {
- def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA_NoExcept<RetClass, Op1Class, Constraint>;
+ def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_NoExcept<RetClass, Op1Class, Constraint>;
}
}
@@ -3976,31 +3976,11 @@ class VPatUnaryMask<string intrinsic_name,
ValueType result_type,
ValueType op2_type,
ValueType mask_type,
- int sew,
+ int log2sew,
LMULInfo vlmul,
VReg result_reg_class,
- VReg op2_reg_class> :
- Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
- (result_type result_reg_class:$merge),
- (op2_type op2_reg_class:$rs2),
- (mask_type V0),
- VLOpFrag)),
- (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
- (result_type result_reg_class:$merge),
- (op2_type op2_reg_class:$rs2),
- (mask_type V0), GPR:$vl, sew)>;
-
-class VPatUnaryMaskTA<string intrinsic_name,
- string inst,
- string kind,
- ValueType result_type,
- ValueType op2_type,
- ValueType mask_type,
- int log2sew,
- LMULInfo vlmul,
- VReg result_reg_class,
- VReg op2_reg_class,
- bit isSEWAware = 0> :
+ VReg op2_reg_class,
+ bit isSEWAware = 0> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
(result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2),
@@ -4502,8 +4482,8 @@ multiclass VPatUnaryV_M<string intrinsic, string instruction>
vti.Log2SEW, vti.LMul, VR>;
def : VPatUnaryNoMaskTU<intrinsic, instruction, "M", vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,VR>;
- def : VPatUnaryMaskTA<intrinsic, instruction, "M", vti.Vector, vti.Mask,
- vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
+ def : VPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
+ vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
}
}
}
@@ -4523,9 +4503,9 @@ multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix,
def : VPatUnaryNoMaskTU<intrinsic, instruction, suffix,
vti.Vector, fti.Vector,
vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>;
- def : VPatUnaryMaskTA<intrinsic, instruction, suffix,
- vti.Vector, fti.Vector, vti.Mask,
- vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>;
+ def : VPatUnaryMask<intrinsic, instruction, suffix,
+ vti.Vector, fti.Vector, vti.Mask,
+ vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>;
}
}
}
@@ -4540,9 +4520,9 @@ multiclass VPatUnaryV_V<string intrinsic, string instruction,
def : VPatUnaryNoMaskTU<intrinsic, instruction, "V",
vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;
- def : VPatUnaryMaskTA<intrinsic, instruction, "V",
- vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
- vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;
+ def : VPatUnaryMask<intrinsic, instruction, "V",
+ vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
+ vti.LMul, vti.RegClass, vti.RegClass, isSEWAware>;
}
}
}
@@ -4750,8 +4730,8 @@ multiclass VPatConversionTA<string intrinsic,
sew, vlmul, op1_reg_class>;
def : VPatUnaryNoMaskTU<intrinsic, inst, kind, result_type, op1_type,
sew, vlmul, result_reg_class, op1_reg_class>;
- def : VPatUnaryMaskTA<intrinsic, inst, kind, result_type, op1_type,
- mask_type, sew, vlmul, result_reg_class, op1_reg_class>;
+ def : VPatUnaryMask<intrinsic, inst, kind, result_type, op1_type,
+ mask_type, sew, vlmul, result_reg_class, op1_reg_class>;
}
multiclass VPatBinaryV_VV<string intrinsic, string instruction,
More information about the llvm-commits
mailing list