[llvm] 75b1054 - [RISCV] Combine VPseudoUnaryMask and VPseudoUnaryMaskTA [NFC]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 26 08:24:14 PDT 2023
Author: Philip Reames
Date: 2023-06-26T08:23:48-07:00
New Revision: 75b1054024049956196d97303f2822c33a5e7438
URL: https://github.com/llvm/llvm-project/commit/75b1054024049956196d97303f2822c33a5e7438
DIFF: https://github.com/llvm/llvm-project/commit/75b1054024049956196d97303f2822c33a5e7438.diff
LOG: [RISCV] Combine VPseudoUnaryMask and VPseudoUnaryMaskTA [NFC]
The only difference between these classes was the existance of a policy operand on the later. We can use the policy operand version for the one place which used the non-TA suffixed one. I then renamed to remove TA as these aren't tail agnostic; they take their policy from the operand.
Note that this wouldn't be strictly NFC except that the one user of the class being removed wasn't in the masked psuedo table, and thus doesn't go through mask to unmasked conversion in ISEL. That's a missed optimization we may want to fix at some point.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index befc949f34e89..9b86ce5967843 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1054,20 +1054,6 @@ class VPseudoUnaryNoMaskTU<DAGOperand RetClass, DAGOperand OpClass,
}
class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
- Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
- VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
- RISCVVPseudo {
- let mayLoad = 0;
- let mayStore = 0;
- let hasSideEffects = 0;
- let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
- let HasVLOp = 1;
- let HasSEWOp = 1;
- let UsesMaskPolicy = 1;
-}
-
-class VPseudoUnaryMaskTA<VReg RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
@@ -1973,7 +1959,7 @@ multiclass VPseudoVIOT_M {
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
def "_" # m.MX # "_TU" : VPseudoUnaryNoMaskTU<m.vrclass, VR, constraint>,
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
- def "_" # m.MX # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, VR, constraint>,
+ def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
}
@@ -2391,7 +2377,7 @@ multiclass VPseudoVCLS_V {
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
def "_V_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
- def "_V_" # mx # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, m.vrclass>,
+ def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
}
@@ -2415,7 +2401,7 @@ multiclass VPseudoVSQR_V {
def "_V" # suffix # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
ReadVMask]>;
- def "_V" # suffix # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, m.vrclass>,
+ def "_V" # suffix # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
ReadVMask]>;
@@ -2434,7 +2420,7 @@ multiclass VPseudoVRCP_V {
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
def "_V_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
- def "_V_" # mx # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, m.vrclass>,
+ def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
}
@@ -2455,7 +2441,7 @@ multiclass PseudoVEXT_VF2 {
def "_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f2vrclass, constraints>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" :
- VPseudoUnaryMaskTA<m.vrclass, m.f2vrclass, constraints>,
+ VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
@@ -2476,7 +2462,7 @@ multiclass PseudoVEXT_VF4 {
def "_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f4vrclass, constraints>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" :
- VPseudoUnaryMaskTA<m.vrclass, m.f4vrclass, constraints>,
+ VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
@@ -2497,7 +2483,7 @@ multiclass PseudoVEXT_VF8 {
def "_" # mx # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f8vrclass, constraints>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" :
- VPseudoUnaryMaskTA<m.vrclass, m.f8vrclass, constraints>,
+ VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
@@ -3571,8 +3557,8 @@ multiclass VPseudoConversion<VReg RetClass,
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_TU": VPseudoUnaryNoMaskTU<RetClass, Op1Class, Constraint>;
- def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA<RetClass, Op1Class,
- Constraint>,
+ def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
+ Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
}
}
@@ -4049,7 +4035,7 @@ class VPatMaskUnaryMask<string intrinsic_name,
(!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK")
(mti.Mask VR:$merge),
(mti.Mask VR:$rs2),
- (mti.Mask V0), GPR:$vl, mti.Log2SEW)>;
+ (mti.Mask V0), GPR:$vl, mti.Log2SEW, TU_MU)>;
class VPatUnaryAnyMask<string intrinsic,
string inst,
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