[llvm] 391a95f - [NFC] Autogenerate CodeGen/AMDGPU/combine-reg-or-const.ll

[Amaury Séchet via llvm-commits]

Author: Amaury Séchet
Date: 2023-06-25T22:56:42Z
New Revision: 391a95fdb18e18c784a24ee4eb9412abe0a52e72

URL: https://github.com/llvm/llvm-project/commit/391a95fdb18e18c784a24ee4eb9412abe0a52e72
DIFF: https://github.com/llvm/llvm-project/commit/391a95fdb18e18c784a24ee4eb9412abe0a52e72.diff

LOG: [NFC] Autogenerate CodeGen/AMDGPU/combine-reg-or-const.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
index 8c0486df1c758..3a7100c5903eb 100644
--- a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll
@@ -1,15 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc  -mtriple=amdgcn-amd-amdhsa -o - %s | FileCheck %s
 
 ; The OR instruction should not be eliminated by the "OR Combine" DAG optimization.
-
-; CHECK-LABEL: _Z11test_kernelPii:
-; CHECK: s_mul_i32
-; CHECK: s_sub_i32
-; CHECK: s_and_b32 [[S1:s[0-9]+]], {{s[0-9]+}}, 0xffff
-; CHECK: s_add_i32 [[S2:s[0-9]+]], {{s[0-9]+}}, [[S1]]
-; CHECK: s_or_b32 {{s[0-9]+}}, [[S2]], 0xc0
-
 define protected amdgpu_kernel void @_Z11test_kernelPii(ptr addrspace(1) nocapture %Ad.coerce, i32 %s) local_unnamed_addr #5 {
+; CHECK-LABEL: _Z11test_kernelPii:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    s_load_dword s0, s[4:5], 0x2
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_cmp_lg_u32 s0, 3
+; CHECK-NEXT:    s_cbranch_scc1 .LBB0_2
+; CHECK-NEXT:  ; %bb.1: ; %if.then
+; CHECK-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x0
+; CHECK-NEXT:    s_and_b32 s4, s0, 0xffff
+; CHECK-NEXT:    s_mov_b32 s1, 0
+; CHECK-NEXT:    s_mul_i32 s6, s4, 0xaaab
+; CHECK-NEXT:    s_lshl_b64 s[4:5], s[0:1], 2
+; CHECK-NEXT:    s_lshr_b32 s1, s6, 19
+; CHECK-NEXT:    s_mul_i32 s1, s1, 12
+; CHECK-NEXT:    s_sub_i32 s6, s0, s1
+; CHECK-NEXT:    s_and_b32 s7, s6, 0xffff
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_add_u32 s0, s2, s4
+; CHECK-NEXT:    s_addc_u32 s1, s3, s5
+; CHECK-NEXT:    s_bfe_u32 s2, s6, 0xd0003
+; CHECK-NEXT:    s_add_i32 s2, s2, s7
+; CHECK-NEXT:    s_or_b32 s2, s2, 0xc0
+; CHECK-NEXT:    v_mov_b32_e32 v0, s0
+; CHECK-NEXT:    v_mov_b32_e32 v1, s1
+; CHECK-NEXT:    v_mov_b32_e32 v2, s2
+; CHECK-NEXT:    flat_store_dword v[0:1], v2
+; CHECK-NEXT:  .LBB0_2: ; %if.end
+; CHECK-NEXT:    s_endpgm
 entry:
   %cmp = icmp eq i32 %s, 3
   br i1 %cmp, label %if.then, label %if.end