[llvm] 93af6bd - [NFC] Autogenerate CodeGen/PowerPC/select-i1-vs-i1.ll
Amaury Séchet via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 24 18:29:22 PDT 2023
Author: Amaury Séchet
Date: 2023-06-25T01:27:29Z
New Revision: 93af6bdcaf4d499e9d4c1da5aa82f92f0acc1dbd
URL: https://github.com/llvm/llvm-project/commit/93af6bdcaf4d499e9d4c1da5aa82f92f0acc1dbd
DIFF: https://github.com/llvm/llvm-project/commit/93af6bdcaf4d499e9d4c1da5aa82f92f0acc1dbd.diff
LOG: [NFC] Autogenerate CodeGen/PowerPC/select-i1-vs-i1.ll
Added:
Modified:
llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
index 9f458ebcf0a6e..2efd88d3f7cef 100644
--- a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
+++ b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs -tail-dup-placement=false < %s | FileCheck %s
; RUN: llc -ppc-reduce-cr-logicals -verify-machineinstrs \
; RUN: -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
@@ -9,6 +10,26 @@ target triple = "powerpc64-unknown-linux-gnu"
; can't do so without introducing a register-allocation dependency.
define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: crandc 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32slt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crandc 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -16,22 +37,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-LABEL: @testi32slt
-; CHECK-NO-ISEL-LABEL: @testi32slt
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: crandc 20, 2, 6
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32ult:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crandc 20, 2, 6
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB1_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB1_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -39,21 +67,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-NO-ISEL-LABEL: @testi32ult
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: crorc 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32sle:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crorc 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB2_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB2_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -61,22 +97,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-LABEL: @testi32sle
-; CHECK-NO-ISEL-LABEL: @testi32sle
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: crorc 20, 2, 6
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32ule:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crorc 20, 2, 6
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB3_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB3_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -84,22 +127,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-LABEL: @testi32ule
-; CHECK-NO-ISEL-LABEL: @testi32ule
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: creqv 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32eq:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: creqv 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB4_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB4_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -107,22 +157,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-LABEL: @testi32eq
-; CHECK-NO-ISEL-LABEL: @testi32eq
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: crorc 20, 2, 6
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32sge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crorc 20, 2, 6
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB5_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB5_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -130,22 +187,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-LABEL: @testi32sge
-; CHECK-NO-ISEL-LABEL: @testi32sge
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: crorc 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32uge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crorc 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB6_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB6_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -153,22 +217,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-LABEL: @testi32uge
-; CHECK-NO-ISEL-LABEL: @testi32uge
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: crandc 20, 2, 6
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32sgt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crandc 20, 2, 6
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB7_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB7_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -176,22 +247,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-LABEL: @testi32sgt
-; CHECK-NO-ISEL-LABEL: @testi32sgt
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: crandc 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32ugt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crandc 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB8_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB8_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -199,22 +277,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-LABEL: @testi32ugt
-; CHECK-NO-ISEL-LABEL: @testi32ugt
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+; CHECK-LABEL: testi32ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpw 5, 6
+; CHECK-NEXT: cmpw 1, 3, 4
+; CHECK-NEXT: crxor 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32ne:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpw 5, 6
+; CHECK-NO-ISEL-NEXT: cmpw 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crxor 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB9_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB9_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2
@@ -222,22 +307,29 @@ entry:
%cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond
-; CHECK-LABEL: @testi32ne
-; CHECK-NO-ISEL-LABEL: @testi32ne
-; CHECK-DAG: cmpw 5, 6
-; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
-; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: crandc 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64slt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crandc 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB10_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB10_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -245,22 +337,29 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64slt
-; CHECK-NO-ISEL-LABEL: @testi64slt
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: crandc 20, 2, 6
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64ult:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crandc 20, 2, 6
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB11_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB11_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -268,22 +367,29 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64ult
-; CHECK-NO-ISEL-LABEL: @testi64ult
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: crorc 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64sle:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crorc 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB12_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB12_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -291,22 +397,29 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64sle
-; CHECK-NO-ISEL-LABEL: @testi64sle
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: crorc 20, 2, 6
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64ule:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crorc 20, 2, 6
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB13_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB13_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -314,22 +427,29 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64ule
-; CHECK-NO-ISEL-LABEL: @testi64ule
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: creqv 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64eq:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: creqv 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB14_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB14_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -337,22 +457,29 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64eq
-; CHECK-NO-ISEL-LABEL: @testi64eq
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: crorc 20, 2, 6
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64sge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crorc 20, 2, 6
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB15_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB15_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -360,22 +487,29 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64sge
-; CHECK-NO-ISEL-LABEL: @testi64sge
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: crorc 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64uge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crorc 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB16_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB16_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -383,22 +517,29 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64uge
-; CHECK-NO-ISEL-LABEL: @testi64uge
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: crandc 20, 2, 6
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64sgt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crandc 20, 2, 6
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB17_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB17_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -406,22 +547,29 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64sgt
-; CHECK-NO-ISEL-LABEL: @testi64sgt
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: crandc 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64ugt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crandc 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB18_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB18_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -429,22 +577,29 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64ugt
-; CHECK-NO-ISEL-LABEL: @testi64ugt
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+; CHECK-LABEL: testi64ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpd 5, 6
+; CHECK-NEXT: cmpd 1, 3, 4
+; CHECK-NEXT: crxor 20, 6, 2
+; CHECK-NEXT: isel 3, 7, 8, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi64ne:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: cmpd 5, 6
+; CHECK-NO-ISEL-NEXT: cmpd 1, 3, 4
+; CHECK-NO-ISEL-NEXT: crxor 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB19_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: ori 3, 8, 0
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB19_2: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = icmp eq i64 %c3, %c4
%cmp3tmp = icmp eq i64 %c1, %c2
@@ -452,22 +607,36 @@ entry:
%cond = select i1 %cmp3, i64 %a1, i64 %a2
ret i64 %cond
-; CHECK-LABEL: @testi64ne
-; CHECK-NO-ISEL-LABEL: @testi64ne
-; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
-; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
-; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: isel 3, 7, 8, [[REG1]]
-; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 3, 8, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloatslt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB20_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 12, 2, .LBB20_3
+; CHECK-NEXT: .LBB20_2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB20_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloatslt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB20_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB20_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB20_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -475,19 +644,36 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloatslt
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
-; CHECK: .LBB[[BB1]]:
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB2]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloatult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB21_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 4, 2, .LBB21_3
+; CHECK-NEXT: .LBB21_2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB21_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloatult:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB21_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB21_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB21_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -495,19 +681,34 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloatult
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
-; CHECK: .LBB[[BB1]]:
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB2]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloatsle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB22_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 12, 2, .LBB22_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB22_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloatsle:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB22_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB22_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: .LBB22_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -515,18 +716,34 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloatsle
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloatule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB23_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 4, 2, .LBB23_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB23_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloatule:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB23_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB23_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: .LBB23_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -534,18 +751,30 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloatule
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloateq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: fcmpu 1, 1, 2
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: creqv 20, 6, 2
+; CHECK-NEXT: bclr 12, 20, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fmr 1, 6
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloateq:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 1, 2
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: creqv 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 6
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -553,16 +782,34 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloateq
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: fmr 1, 6
-; CHECK: blr
}
define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloatsge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB25_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 4, 2, .LBB25_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB25_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloatsge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB25_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB25_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: .LBB25_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -570,18 +817,34 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloatsge
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloatuge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB26_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 12, 2, .LBB26_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB26_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloatuge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB26_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB26_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: .LBB26_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -589,18 +852,36 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloatuge
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloatsgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB27_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 4, 2, .LBB27_3
+; CHECK-NEXT: .LBB27_2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB27_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloatsgt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB27_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB27_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB27_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -608,19 +889,36 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloatsgt
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
-; CHECK: .LBB[[BB1]]:
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB2]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloatugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB28_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 12, 2, .LBB28_3
+; CHECK-NEXT: .LBB28_2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB28_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloatugt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB28_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB28_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB28_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -628,19 +926,30 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloatugt
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
-; CHECK: .LBB[[BB1]]:
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB2]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+; CHECK-LABEL: testfloatne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: fcmpu 1, 1, 2
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: crxor 20, 6, 2
+; CHECK-NEXT: bclr 12, 20, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fmr 1, 6
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testfloatne:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 1, 2
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: crxor 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 6
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -648,16 +957,36 @@ entry:
%cond = select i1 %cmp3, float %a1, float %a2
ret float %cond
-; CHECK-LABEL: @testfloatne
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: fmr 1, 6
-; CHECK: blr
}
define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoubleslt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB30_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 12, 2, .LBB30_3
+; CHECK-NEXT: .LBB30_2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB30_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoubleslt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB30_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB30_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB30_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -665,19 +994,36 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoubleslt
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
-; CHECK: .LBB[[BB1]]:
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB2]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoubleult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB31_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 4, 2, .LBB31_3
+; CHECK-NEXT: .LBB31_2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB31_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoubleult:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB31_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB31_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB31_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -685,19 +1031,34 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoubleult
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
-; CHECK: .LBB[[BB1]]:
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB2]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoublesle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB32_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 12, 2, .LBB32_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB32_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoublesle:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB32_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB32_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: .LBB32_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -705,18 +1066,34 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoublesle
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoubleule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB33_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 4, 2, .LBB33_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB33_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoubleule:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB33_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB33_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: .LBB33_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -724,18 +1101,30 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoubleule
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoubleeq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: fcmpu 1, 1, 2
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: creqv 20, 6, 2
+; CHECK-NEXT: bclr 12, 20, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fmr 1, 6
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoubleeq:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 1, 2
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: creqv 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 6
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -743,16 +1132,34 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoubleeq
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: fmr 1, 6
-; CHECK: blr
}
define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoublesge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB35_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 4, 2, .LBB35_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB35_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoublesge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB35_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB35_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: .LBB35_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -760,18 +1167,34 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoublesge
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoubleuge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB36_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 12, 2, .LBB36_3
+; CHECK-NEXT: # %bb.2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB36_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoubleuge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB36_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB36_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: .LBB36_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -779,18 +1202,36 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoubleuge
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoublesgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB37_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 4, 2, .LBB37_3
+; CHECK-NEXT: .LBB37_2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB37_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoublesgt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB37_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB37_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB37_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -798,19 +1239,36 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoublesgt
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 4, 2, .LBB[[BB2:[0-9_]+]]
-; CHECK: .LBB[[BB1]]:
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB2]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoubleugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB38_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bc 12, 2, .LBB38_3
+; CHECK-NEXT: .LBB38_2: # %entry
+; CHECK-NEXT: fmr 5, 6
+; CHECK-NEXT: .LBB38_3: # %entry
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoubleugt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB38_3
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB38_3
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB38_3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 5, 6
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -818,19 +1276,30 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoubleugt
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB1:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bc 12, 2, .LBB[[BB2:[0-9_]+]]
-; CHECK: .LBB[[BB1]]:
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB2]]:
-; CHECK: fmr 1, 5
-; CHECK: blr
}
define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+; CHECK-LABEL: testdoublene:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: fcmpu 1, 1, 2
+; CHECK-NEXT: fmr 1, 5
+; CHECK-NEXT: crxor 20, 6, 2
+; CHECK-NEXT: bclr 12, 20, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fmr 1, 6
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testdoublene:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 1, 2
+; CHECK-NO-ISEL-NEXT: fmr 1, 5
+; CHECK-NO-ISEL-NEXT: crxor 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 6
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq double %c3, %c4
%cmp3tmp = fcmp oeq double %c1, %c2
@@ -838,16 +1307,30 @@ entry:
%cond = select i1 %cmp3, double %a1, double %a2
ret double %cond
-; CHECK-LABEL: @testdoublene
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: fmr 1, 6
-; CHECK: blr
}
define <4 x float> @testv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floatslt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB40_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: .LBB40_2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floatslt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB40_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: .LBB40_2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -855,17 +1338,30 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floatslt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 12, 2, 0
-; CHECK: .LBB[[BB]]:
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floatult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB41_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: .LBB41_2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floatult:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB41_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: .LBB41_2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -873,17 +1369,30 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floatult
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 4, 2, 0
-; CHECK: .LBB[[BB]]:
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floatsle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # %bb.2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floatsle:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -891,16 +1400,30 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floatsle
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bclr 4, 2, 0
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 12, 2, 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floatule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: # %bb.2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floatule:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -908,16 +1431,28 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floatule
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bclr 12, 2, 0
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 4, 2, 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floateq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: fcmpu 1, 1, 2
+; CHECK-NEXT: creqv 20, 6, 2
+; CHECK-NEXT: bclr 12, 20, 0
+; CHECK-NEXT: # %bb.1: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floateq:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 1, 2
+; CHECK-NO-ISEL-NEXT: creqv 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -925,16 +1460,30 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floateq
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floatsge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: # %bb.2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floatsge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -942,16 +1491,30 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floatsge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bclr 12, 2, 0
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 4, 2, 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floatuge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # %bb.2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floatuge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -959,16 +1522,30 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floatuge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bclr 4, 2, 0
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 12, 2, 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floatsgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB47_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: .LBB47_2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floatsgt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB47_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: .LBB47_2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -976,16 +1553,30 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floatsgt
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB1:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 4, 2, 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floatugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB48_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: .LBB48_2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floatugt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB48_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: .LBB48_2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -993,17 +1584,28 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floatugt
-; CHECK: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
-; CHECK: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 12, 2, 0
-; CHECK: .LBB[[BB]]
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+; CHECK-LABEL: testv4floatne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: fcmpu 1, 1, 2
+; CHECK-NEXT: crxor 20, 6, 2
+; CHECK-NEXT: bclr 12, 20, 0
+; CHECK-NEXT: # %bb.1: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv4floatne:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 1, 2
+; CHECK-NO-ISEL-NEXT: crxor 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1011,16 +1613,50 @@ entry:
%cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
ret <4 x float> %cond
-; CHECK-LABEL: @testv4floatne
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 {
+; CHECK-LABEL: testppc_fp128eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 6, 8
+; CHECK-NEXT: fcmpu 1, 5, 7
+; CHECK-NEXT: fcmpu 5, 2, 4
+; CHECK-NEXT: fcmpu 6, 1, 3
+; CHECK-NEXT: crand 20, 6, 2
+; CHECK-NEXT: crand 21, 26, 22
+; CHECK-NEXT: crxor 20, 21, 20
+; CHECK-NEXT: bc 12, 20, .LBB50_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fmr 11, 9
+; CHECK-NEXT: .LBB50_2: # %entry
+; CHECK-NEXT: bc 12, 20, .LBB50_4
+; CHECK-NEXT: # %bb.3: # %entry
+; CHECK-NEXT: fmr 12, 10
+; CHECK-NEXT: .LBB50_4: # %entry
+; CHECK-NEXT: fmr 1, 11
+; CHECK-NEXT: fmr 2, 12
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testppc_fp128eq:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 6, 8
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 5, 7
+; CHECK-NO-ISEL-NEXT: fcmpu 5, 2, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 6, 1, 3
+; CHECK-NO-ISEL-NEXT: crand 20, 6, 2
+; CHECK-NO-ISEL-NEXT: crand 21, 26, 22
+; CHECK-NO-ISEL-NEXT: crxor 20, 21, 20
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB50_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 11, 9
+; CHECK-NO-ISEL-NEXT: .LBB50_2: # %entry
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB50_4
+; CHECK-NO-ISEL-NEXT: # %bb.3: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 12, 10
+; CHECK-NO-ISEL-NEXT: .LBB50_4: # %entry
+; CHECK-NO-ISEL-NEXT: fmr 1, 11
+; CHECK-NO-ISEL-NEXT: fmr 2, 12
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq ppc_fp128 %c3, %c4
%cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2
@@ -1032,26 +1668,30 @@ entry:
; works, we end up with two blocks with the same predicate. These could be
; combined.
-; CHECK-LABEL: @testppc_fp128eq
-; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8
-; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7
-; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3
-; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: crxor [[REG3:[0-9]+]], [[REG2]], [[REG1]]
-; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]]
-; CHECK: fmr 11, 9
-; CHECK: .LBB[[BB1]]:
-; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]]
-; CHECK: fmr 12, 10
-; CHECK: .LBB[[BB2]]:
-; CHECK-DAG: fmr 1, 11
-; CHECK-DAG: fmr 2, 12
-; CHECK: blr
}
define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doubleslt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB51_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: .LBB51_2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doubleslt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB51_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: .LBB51_2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1059,17 +1699,30 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doubleslt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 12, 2, 0
-; CHECK: .LBB[[BB]]:
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doubleult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB52_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: .LBB52_2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doubleult:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB52_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: .LBB52_2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1077,17 +1730,30 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doubleult
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 4, 2, 0
-; CHECK: .LBB[[BB]]:
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doublesle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # %bb.2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doublesle:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1095,16 +1761,30 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doublesle
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bclr 4, 2, 0
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 12, 2, 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doubleule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: # %bb.2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doubleule:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1112,16 +1792,28 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doubleule
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bclr 12, 2, 0
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 4, 2, 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doubleeq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: fcmpu 1, 1, 2
+; CHECK-NEXT: creqv 20, 6, 2
+; CHECK-NEXT: bclr 12, 20, 0
+; CHECK-NEXT: # %bb.1: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doubleeq:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 1, 2
+; CHECK-NO-ISEL-NEXT: creqv 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1129,16 +1821,30 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doubleeq
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doublesge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: # %bb.2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doublesge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1146,16 +1852,30 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doublesge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bclr 12, 2, 0
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 4, 2, 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doubleuge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: # %bb.2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doubleuge:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: # %bb.2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1163,16 +1883,30 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doubleuge
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bclr 4, 2, 0
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 12, 2, 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doublesgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 4, 2, .LBB58_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 4, 2, 0
+; CHECK-NEXT: .LBB58_2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doublesgt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 4, 2, .LBB58_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 4, 2, 0
+; CHECK-NO-ISEL-NEXT: .LBB58_2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1180,17 +1914,30 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doublesgt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 4, 2, .LBB[[BB:[0-9_]+]]
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 4, 2, 0
-; CHECK: .LBB[[BB]]
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doubleugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: bc 12, 2, .LBB59_2
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: fcmpu 0, 1, 2
+; CHECK-NEXT: bclr 12, 2, 0
+; CHECK-NEXT: .LBB59_2: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doubleugt:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: bc 12, 2, .LBB59_2
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 1, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 2, 0
+; CHECK-NO-ISEL-NEXT: .LBB59_2: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1198,17 +1945,28 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doubleugt
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK: bc 12, 2, .LBB[[BB:[0-9_]+]]
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: bclr 12, 2, 0
-; CHECK: .LBB[[BB]]
-; CHECK: vmr 2, 3
-; CHECK: blr
}
define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+; CHECK-LABEL: testv2doublene:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: fcmpu 0, 3, 4
+; CHECK-NEXT: fcmpu 1, 1, 2
+; CHECK-NEXT: crxor 20, 6, 2
+; CHECK-NEXT: bclr 12, 20, 0
+; CHECK-NEXT: # %bb.1: # %select.false
+; CHECK-NEXT: vmr 2, 3
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testv2doublene:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: fcmpu 0, 3, 4
+; CHECK-NO-ISEL-NEXT: fcmpu 1, 1, 2
+; CHECK-NO-ISEL-NEXT: crxor 20, 6, 2
+; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
+; CHECK-NO-ISEL-NEXT: # %bb.1: # %select.false
+; CHECK-NO-ISEL-NEXT: vmr 2, 3
+; CHECK-NO-ISEL-NEXT: blr
entry:
%cmp1 = fcmp oeq float %c3, %c4
%cmp3tmp = fcmp oeq float %c1, %c2
@@ -1216,13 +1974,6 @@ entry:
%cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
ret <2 x double> %cond
-; CHECK-LABEL: @testv2doublene
-; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
-; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vmr 2, 3
-; CHECK: blr
}
attributes #0 = { nounwind readnone "target-cpu"="pwr7" }
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