[llvm] 8412a17 - [NFC] Autogenerate CodeGen/ARM/2013-07-29-vector-or-combine.ll

[Amaury Séchet via llvm-commits]

Author: Amaury Séchet
Date: 2023-06-25T01:05:21Z
New Revision: 8412a17b79c76911ace8dd4eb028ad7255dbb561

URL: https://github.com/llvm/llvm-project/commit/8412a17b79c76911ace8dd4eb028ad7255dbb561
DIFF: https://github.com/llvm/llvm-project/commit/8412a17b79c76911ace8dd4eb028ad7255dbb561.diff

LOG: [NFC] Autogenerate CodeGen/ARM/2013-07-29-vector-or-combine.ll

Added: 
    

Modified: 
    llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll b/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
index 59a774aa13f7b..5e48b295ef141 100644
--- a/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
+++ b/llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc < %s -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 | FileCheck %s
 ; ModuleID = 'bugpoint-reduced-simplified.bc'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
@@ -5,15 +6,30 @@ target triple = "armv7--linux-gnueabi"
 
 ; CHECK-LABEL: function
 define void @function() {
-; CHECK: cmp r0, #0
-; CHECK: bxne lr
+; CHECK-LABEL: function:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    bxne lr
+; CHECK-NEXT:  .LBB0_1: @ %vector.body
+; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vld1.32 {d16, d17}, [r0]
+; CHECK-NEXT:    adr r0, .LCPI0_0
+; CHECK-NEXT:    vbic.i32 q8, #0xff
+; CHECK-NEXT:    vld1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT:    vorr q8, q8, q9
+; CHECK-NEXT:    vst1.32 {d16, d17}, [r0]
+; CHECK-NEXT:    b .LBB0_1
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  @ %bb.2:
+; CHECK-NEXT:  .LCPI0_0:
+; CHECK-NEXT:    .long 1 @ 0x1
+; CHECK-NEXT:    .long 2 @ 0x2
+; CHECK-NEXT:    .long 3 @ 0x3
+; CHECK-NEXT:    .long 4 @ 0x4
 entry:
   br i1 undef, label %vector.body, label %for.end
 
-; CHECK: vld1.32 {d16, d17}, [r0]
-; CHECK: vbic.i32 q8, #0xff
-; CHECK: vorr q8, q8, q9
-; CHECK: vst1.32 {d16, d17}, [r0]
 vector.body:
   %wide.load = load <4 x i32>, ptr undef, align 4
   %0 = and <4 x i32> %wide.load, <i32 -16711936, i32 -16711936, i32 -16711936, i32 -16711936>