[PATCH] D153620: [X86] Combine MUL+SRL+TRUNC to MULX for i32 on 64-bit

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5284
+  if (VT.isSimple() && !VT.isVector() &&
+      !TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
     MVT Simple = VT.getSimpleVT();
----------------
Shouldn't this be SMUL_LOHI?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153620/new/

https://reviews.llvm.org/D153620